Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-04-04
2009-10-27
Jacques, Jacques H. Louis (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S734000, C714S030000
Reexamination Certificate
active
07610537
ABSTRACT:
A computer implemented method, data processing system, and computer usable code are provided for testing multi-core microprocessors. A test process initiates testing on communication bus interfaces associated with a set of processor cores on the multiprocessor in which the communication bus interfaces are disabled and wherein the testing uses a set of isolation test sequences to obtain results. The process identifies a set of functional processor cores in the set of processor cores based upon the results. The process also initiates a ramp logic built-in self-test to test a ramp associated with a functional processor core in the set of functional processor cores, wherein the ramp logic built-in self-test determines if the communication bus interface associated with functional processor core in the set of functional processor cores is functional.
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Dickinson Dan Jeffrey
Kenney Robert D.
Newman-LaBounty Christina Lynne
Walther Ronald Gene
International Business Machines - Corporation
Jacques Jacques H. Louis
Tabone, Jr. John J
Talpis Matthew B.
Yee & Associates P.C.
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