Method and apparatus for testing memory

Details Method and apparatus for testing memory Method and apparatus for testing memory

1999-09-23

2003-12-30

Chung, Phung M. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06671836

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to the field of semiconductor memory testing, and more particularly, to the testing of dynamic random access memory (DRAM).
BACKGROUND OF THE INVENTION
There is a need to test dynamic random access memories (DRAMs) to ensure that the device operates properly according to the specification. The methods most commonly employed for testing DRAM involve writing a string of 1's or 0's into every address space and then reading from every address space. Another method involves writing a specific pattern of 1's and 0's, for example a checker board pattern, into every address space, then reading from every address space.
One disadvantage of this process is that it is slow. It takes time to write to and read from every address space of a large DRAM. Another disadvantage is that there are certain errors that cannot be detected by this method. It is desirable to have a memory testing apparatus and method that can detect as many errors as possible.
SUMMARY AND OBJECTS OF THE INVENTION
In view of the limitations of known memory and methods of testing memory, one of the objects of the present invention is to provide an improved method and apparatus for allowing a user to “see” inside a memory device without probing.
Another object of the present invention is to provide an improved method and apparatus for performing tests on protocol based memories.
These and other objects of the invention are provided for by a method and apparatus for a test mode for memory testing. A memory is described. The memory has a plurality of pins. The memory also has a memory core. A memory interface receives a signal to reconfigure the functionality of the interface to provide a direct path between the plurality of pins and the memory core.


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