Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-04-28
1999-10-19
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
327 90, G01R 3128
Patent
active
059681918
ABSTRACT:
A method and apparatus is disclosed for testing integrated circuit interconnect and measuring the value of passive component interconnecting the IC's. Each IC includes both analog and digital circuitry and is provided with a test access port and boundary scan architecture for selectively connecting components to an analog test bus and for testing for the integrity of interconnections. When connected with the test bus, a constant current is supplied to the component and the resulting voltage developed across the bus is used for identifying the value of the component. In a second embodiment each IC includes a pair of buses which permits measurement of the impedance of the switches connecting the components to the test bus.
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McDermid John Elliott
Oresjo Stig Herman
Parker Kenneth Paul
Thatcher Carl Wilmer
Beausoliel, Jr. Robert W.
Ford Motor Company
Hewlett--Packard Company
Iqbal Nadeem
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