Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-06-08
2002-04-30
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
06381722
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuits and, more specifically, to the testing of high speed input paths in integrated circuits.
BACKGROUND
Test systems are used to evaluate integrated circuits to determine whether the integrated circuits meet manufacturing and design specifications. An integrated circuit is tested by connecting a test system to pads located on the integrated circuit. The integrated circuit is subjected to functional and parametric testing. Some of the testing may include the measurement of key input/output (I/O) timing parameters, such as input data setup and hold times. The tester transmits signals to stimulate the integrated circuit and then measures responses from the integrated circuit. The signals are generated by the tester using edge generators. An edge generator contains driver circuitry to produce a signal having an edge at a certain time relative to start of a timing period. A high resolution edge placement accuracy is required when testing high speed I/O paths. As such, resolution inaccuracies in the tester may effect the measurement of critical I/O timing parameters.
One prior art testing method uses an output buffer and delay element to perform relative I/O timing measurements. One problem with such a testing method is that it is susceptible to signal coupling from adjacent bond pad wires and loading from external elements, resulting in the generation of noise in the tested parameter. Such noise results in measurement inaccuracies that may cause the testing method to be unreliable.
SUMMARY OF THE INVENTION
A method for testing an input data path including determining a maximum for a value of a timing parameter and generating a data pattern with the timing parameter having the maximum value. The data pattern being generated inside the integrated circuit. The method also including monitoring an output of a logic function performed on the data pattern and adjusting the value of the timing parameter based on the output of the logic function. The timing parameter being adjusted inside the integrated circuit.
Additional features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
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Balajee et al. “Automated AC (Timing) Characterization for Digital Circuit Testing” IEEE 1997 pp. 374-377.*
Lee, Thomas H.; Donnelly, Kevin S.; et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,,” IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994.
Maddux John T.
Salmon Joseph H.
Blakely , Sokoloff, Taylor & Zafman LLP
De'cady Albert
Harris C. R.
Intel Corporation
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