Error detection/correction and fault detection/recovery – Pulse or data error handling – Testing of error-check system
Reexamination Certificate
1999-11-23
2003-03-25
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Testing of error-check system
C714S032000, C714S041000
Reexamination Certificate
active
06539503
ABSTRACT:
TECHNICAL FIELD
The invention relates to testing of error detection. More particularly, the invention relates to methods and equipment for testing error detection and/or correction in a program, such as a design simulation of a processor or a similar digital logic device.
BACKGROUND ART
Whenever a new electronic device is designed, it is necessary to test the device to verify that it performs as intended. This is particularly true for electronic devices comprising digital logic circuitry. Because the number of digital logic variables can be large and because each variable can be in a number of states, the possible combinations and permutations of conditions for a digital logic circuit can be enormous. This is especially true for large, complex digital logic circuits, such as processors (including, for example, general purpose microprocessors, mathematical processors or coprocessors, digital signal processors, or other special purpose processors, controllers, microcontrollers, or microprocessors), which, accordingly, present challenges for testing and verification.
An arrangement
100
for testing a design of a digital logic device is illustrated in FIG.
1
. Rather than testing the actual hardware device, the arrangement
100
tests the design of the device using software models and emulations. Device model
105
is a fairly accurate and detailed model of the actual device. Typically, the device model
105
is expressed in a hardware description language (HDL), such as VHDL or Verilog, both of which are known in the art. Initialization test vectors
110
are applied to the device model
105
. The initialization test vectors
110
are internal digital variable values that place the device model
105
into a known initialized state. The initialization test vectors
110
are also applied to a device emulator
115
, which is a simplified functional model of the device. The device emulator
115
differs from the device model
105
in that the device model
105
is a close approximation to the actual device, whereas the device emulator
115
represents only the functionality of the device, as ideally envisioned by the designer. With a predetermined initial condition set by the initialization test vectors
110
, both the device model
105
and the device emulation
115
are simulated in operation. A monitor
120
observes the outputs of the devices
105
and
115
, noting any differences. If differences are present, then the device model
105
has not performed as it was intended to perform, and the design of the device must be modified.
FIG. 2
shows a more particular testing arrangement
200
. In
FIG. 2
, the focus of testing is a subpart of the device, although other portions of the device related to the subpart can also be tested in the arrangement
200
. More specifically, an error detector of the device is the focus of testing. The error detector is capable of detecting, and possibly correcting, some types of data corruption (i.e., errors in data, addresses or other types of values manipulated by the device). Like the general arrangement
100
, the arrangement
200
of
FIG. 2
utilizes a device model
205
and a relatively less sophisticated device emulator
215
. Initialization test vectors
210
are loaded into both the device model
205
and the device emulator
215
to set internal registers, counters and the like to a predetermined state. Then, the operation of both the device model
205
(including an error detector model
225
) and the device emulator
215
are simulated while the checker
220
compares them. To test the error detector model
225
using the arrangement
200
, it is necessary to construct the initialization test vectors
210
appropriately so as to contain detectable errors. The arrangement
200
, while useful, is limited in many respects in its ability to effectively test the error detection section of the device.
SUMMARY OF INVENTION
In one respect, the invention is a method for improved testing of the design of an electronic device comprising digital logic circuitry. The method comprises testing the design of an electronic device and injecting, after initiation of the testing step, a predetermined error pattern into a value operated upon by the design of the digital logic circuitry. In a preferred embodiment, the electronic device is a processor having a cache with error detection and/or correction circuitry, and the design of the processor is tested by simulating operation of the processor using a model. A cache hit is a triggering condition, in response to which a detectable error is injected into the cache. The simulated operations of the model are observed to determine whether the injected error is detected, as should happen if the cache's error detection circuitry has been designed properly.
In another respect, the invention is an apparatus for improved testing of a program comprising an error detector. The apparatus comprises the program, an error injector module connected to the program, and a checker module connected to the program. The checker module determines whether the program responds appropriately to an error dynamically produced by the error injector module during execution of the program.
In yet another respect, the invention is computer software embedded on a computer readable medium. The computer software comprises a software program comprising an error detector, an error injector module connected to the software program, and a checker module connected to the software program—all in software form. The checker module is capable of determining whether the program responds appropriately to an error dynamically produced by the error injector module during execution of the program.
In comparison to the initialization-based testing arrangements, certain embodiments of the present invention are capable of achieving certain advantages, including the following:
(1) Existing components (e.g., initialization test vectors, device models, device emulations, and checker) of the initialization-based testing arrangement can be utilized with little or no modification. Most importantly, large libraries of pre-existing initialization test vectors are already available for use with the present invention.
(2) The present invention is better able to test “comer cases” that arise from “in-flight” operations. In designs employing error correction along with error detection, the initialization-based arrangement can only test a given error condition once, after which the error is typically corrected, never to appear again. The present invention, however, can inject the same error condition after its initial injection, as many times as desired, to test the error detection circuitry under multiple operating scenarios further in-flight.
(3) Testing with greater focus is possible with the present invention, because greater control can be exercised as to when and where to inject errors.
(4) Errors can be injected into data structures that cannot effectively be initialized using initialization test vectors. For example, buffers,queues or the like that get flushed or updated may not be able to hold an initial value long enough to test the error detection circuitry. However, the present invention is not limited to errors present at initialization.
Those skilled in the art will appreciate these and other advantages and benefits of various embodiments of the invention upon reading the following detailed description of a preferred embodiment with reference to the drawings.
REFERENCES:
patent: 5513339 (1996-04-01), Agrawal et al.
patent: 5668816 (1997-09-01), Douskey et al.
patent: 5671352 (1997-09-01), Subrahmaniam et al.
patent: 5822511 (1998-10-01), Kashyap et al.
patent: 5859999 (1999-01-01), Morris et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 5872910 (1999-02-01), Kuslak et al.
patent: 5920490 (1999-07-01), Peters
patent: 6154801 (2000-11-01), Lowe et al.
patent: 2226168 (1990-06-01), None
Wolfe, A., “Patents shed light on Merced's Innards”, Electronic Engineering Times, Feb. 15, 1999. pp. 43-44.
Hewlett--Packard Company
Tu Christine T.
LandOfFree
Method and apparatus for testing error detection does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for testing error detection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing error detection will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3040409