Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1994-10-28
2002-03-05
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000
Reexamination Certificate
active
06353903
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to the testing of differential signals. More particularly, the present invention relates to capturing and providing a true signal and its complement for testing thereof.
2. Background Art
The performance demands on dynamic circuits has led to the use of both true and complement signals, both in the data path and in the testing path. For example, memory chips have been designed requiring not only the actual addresses in the memory array, but also the complement of a given address. In addition, some memory chips also provide true and complement output data to provide a faster interface to attached logic at the array output.
While the need for true/complement signal pairs has increased, testing thereof has largely remained focused on only the true signal and not the complement signal. In the past, testing schemes have focused on generating a complement of the true signal, rather than testing the actual complement, for example, using a latch. However, this type of design ignores the possibility that the actual complement signal may not have the correct signature (i.e., may not be the actual complement of the true signal or may not be the expected signal even if it is the complement of the true signal), or that there may be a physical problem with the complement signal path.
One proposed solution to this problem can be found in U.S. Pat. No. 4,698,830, issued to Barzilai et al. and assigned to IBM.
FIG. 4
of the Barzilai patent depicts data and minus data signals entering testing logic
36
, the purpose of which is to ensure that the data and minus data signals have the correct signature prior to testing. However, logic block
36
contains several logic elements occupying valuable real estate and may be more complex than is necessary to ensure that both the data and minus data signals are able to be tested. A deceptively simple solution to the problem of testing both the true and complement signals is to provide one latch for each signal that could be clocked at different times to provide the signals to the testing logic. However, a latch is a relatively large component and occupies much valuable chip real estate, which explains the use of a single latch both to pass the true signal and to generate a complement signal therefor to the testing logic.
Thus, a need exists for a less complex way to provide a true signal and its complement for testing while minimizing the amount of valuable chip real estate dedicated thereto.
SUMMARY OF THE INVENTION
Briefly, the present invention satisfies the need for a less complex way to provide true/complement pairs for testing without using an excess of valuable chip real estate by multiplexing the true and complement signals for capturing by a latch and providing to testing logic.
In accordance with the above, it is an object of the present invention to provide increased test coverage of differential signals.
It is another object of the present invention to provide both a true signal and a real complement signal for testing.
It is a further object of the present invention to sequentially provide a true signal and its complement for testing.
The present invention provides, in a first aspect, a test circuit, comprising a means for selecting a test signal from among a true signal and a complement signal, and a means for capturing the test signal for testing. The test circuit may further comprise a means for providing the test signal for testing. The selecting means may comprise a true signal line, a complement signal line and a multiplexer for providing the test signal to the capturing means in response to a select signal. The capturing means may comprise a latch. The providing means may also comprise a latch.
The present invention provides, in a second aspect, a method for testing differential signals. The method comprises steps of providing a true signal and a complement signal and selecting a test signal for testing from among the true and complement signals. The method may also include steps of capturing the test signal and providing same for testing. The step of selecting may comprise sequentially selecting the test signal from among the true and complement signals.
These, and other objects, features and advantages of this invention will become apparent from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings.
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Adams Robert Dean
Connor John
Evans Donald Albert
Ternullo, Jr. Luigi
Chadurjian Mark F.
Heslin & Rothenburg, PC
International Business Machines - Corporation
Iqbal Nadeem
Shkurko Eugene I.
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