Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-02-28
2003-07-22
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S744000
Reexamination Certificate
active
06598192
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the testing of integrated circuits (IC), and in particular, the present invention relates to the testing of integrated circuits where certain desired clock waveforms are required to achieve a desired result.
RELATED ART
After an integrated circuit is manufactured, it is put through a series of tests. One of these tests is a scan-based structural test. When performing scan-based structural testing, several problems must be addressed.
One problem relates to the capabilities of the automatic test equipment (ATE), or IC tester. Applying at-speed scan vectors or AC scan vectors requires test equipment that has the ability to apply clock cycles at the speed of the fastest clock specified by the IC being tested. For example, to perform an at-speed test for a 200 MHz IC (for timing verification), a tester must apply a 200 MHz clock cycle. Some testers have the ability to multiplex signals which allows the signals to be applied at twice the rated speed of the tester, but that may still not be fast enough for the speed of some devices. In addition, a tester may also not be able to provide the clock edge-rates (the rate at which the clock signal transitions from low to high, or from high to low) required by some devices. As the speed and precision of testers increases, so does its cost. Since the cost of the tester significantly affects the cost of a tested device, less expensive testers are desired.
Another problem relates to the pads on the integrated circuit. Even if a fast enough and accurate enough tester is available, the capability of the pads may be a problem. The pads may be a limitation that negates the capabilities of the tester. First, pads that can handle the speed of the clock from the tester may not be available. In addition, any signal passing through the pad may be degraded by the pad.
Another problem relates to the power consumed by device during the testing process. When performing scan testing, there is a possibility of a high toggle rate and, therefore, high power consumption. To reduce the power consumed by the integrated circuit during testing, it is desirable to reduce the toggle rate, where the toggle rate includes the number of transitions or the frequency of the data.
It should also be noted that embedded cores have aggressive clocking requirements and are required to be tested for structure and for specifications after they are embedded. This type of testing can not always be done with “functional” vectors since cores have limited access. Therefore, many embedded cores require AC scan for “timing defects” and simple timing specification verification.
Following is a description of one prior art attempt at overcoming some of the problems encountered during scan testing. During scan testing, the launch to capture cycle is the only cycle that tests the functional paths of the device being tested. Therefore, this is the only cycle-to-cycle period that must be applied at the maximum frequency to test the device at its rated speed during scan testing. This prior art attempt assumes that there are two clock domains, the core and the peripheral logic. This prior art testing method uses a methodology, using bypass test clocks, which allows scan data shifting at a slow speed and conducting the functional capture operation at a high speed. This testing method also uses the pin multiplexer timing on the tester.
FIG. 1
is a timing diagram illustrating how the automated test pattern generator (ATPG) clock data can be manipulated in order to create waveforms that test the launch to capture cycle speed.
FIG. 1
shows peripheral and core clock signals
10
and
12
. In addition,
FIG. 1
shows a waveform
14
created such that there is still only one clock per interval, but the correct timing relationship is installed to test the launch to capture cycle at the desired speed. The waveform of the clock signal
14
is controlled based on the core clock pattern data which is also shown in FIG.
1
. It can be seen that there is only one pulse per interval (between the solid lines), but the second pulse
16
(launch) and third pulse
18
(capture) are positioned close to each other to simulate a faster speed. In this way, a device can be tested using a slower tester. However, even with this solution, the pads of the device being tested must be able to handle the fast speed. In addition, even if a tester is fast enough to work under this testing method, when the abilities of a tester are pushed, the tester does not work well close to its limits. Other problems with this approach include insufficient edge rate and high power consumption potential.
REFERENCES:
patent: 5422858 (1995-06-01), Mizukami et al.
patent: 5524114 (1996-06-01), Peng
patent: 6115836 (2000-09-01), Churchill et al.
patent: 6195772 (2001-02-01), Mielke et al.
patent: 6378098 (2002-04-01), Yamashita
Crouch Alfred L.
Mason Kristen L.
McLaurin Teresa L.
Tietjen Donald L.
Clingan, Jr. James L
De'cady Albert
Dooley Matthew C.
Motorola Inc.
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