Method and apparatus for testing an IC device based on...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S055000, C714S700000, C714S815000, C702S089000, C702S125000, C702S176000, C702S177000, C716S030000

Reexamination Certificate

active

07624323

ABSTRACT:
An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for monitoring the test signals input in the IC device and a signal output from the IC device for a predetermined time period, and creating an array indicating an execution or a nonexecution of signal timing combinations of one of the test signals relative to at least one of the other test signals within the predetermined time period by the IC device. A determination as to whether the desired signal timing combinations of the test signals have been executed by the IC device is made by an operator.

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patent: 2007/0061097 (2007-03-01), Sato

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