Method and apparatus for testing an I/O buffer

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S048000

Reexamination Certificate

active

06889350

ABSTRACT:
A buffer circuit is provided having a driver device and an input device to receive a first set of signals and to produce a second set of signals. The driver device may receive the second set of signals and output a third set of signals based on the second set of signals input to said driver device. A comparing device may receive the third set of signals from the driver device and produce a fourth set of signals based on the third set of signals, the comparing device may compare the fourth set of signals with the first set of signals.

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patent: 5646948 (1997-07-01), Kobayashi et al.
patent: 5805601 (1998-09-01), Takeda et al.
patent: 5959487 (1999-09-01), Kawamura
patent: 6512707 (2003-01-01), Miura et al.
patent: 6566857 (2003-05-01), Kakizawa et al.
patent: 6725406 (2004-04-01), Kakizawa et al.
“Delay Test of Chip I/Os Using LSSD Boundary Scan”, Gillis et al., Oct. 18-23, 1998, Test Conference Proceedings 1998, pp 83-90.*
“GTLP16616 17-Bit TTL/GTLP Bus Transceiver With Buffered Clock”, Jun. 1997, Spec Sheet, Fairchild Semiconductor.*
U.S. Appl. No. 10/749,629, Swartz et al., pending, not yet published.

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