Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-05-03
2005-05-03
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S048000
Reexamination Certificate
active
06889350
ABSTRACT:
A buffer circuit is provided having a driver device and an input device to receive a first set of signals and to produce a second set of signals. The driver device may receive the second set of signals and output a third set of signals based on the second set of signals input to said driver device. A comparing device may receive the third set of signals from the driver device and produce a fourth set of signals based on the third set of signals, the comparing device may compare the fourth set of signals with the first set of signals.
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U.S. Appl. No. 10/749,629, Swartz et al., pending, not yet published.
Blodgett Cass A.
Fought Eric T.
Kakizawa Akira
De'cady Albert
Huter Jeffrey B.
Trimmings John P
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