Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-05-16
2006-05-16
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S741000
Reexamination Certificate
active
07047460
ABSTRACT:
A tester or method of testing a mass storage interface queues error functions for simulation responsive to condition criteria of such storage simulation. Such bridge-chip tester may comprise ATA registers to receive data from an ATA or ATAPI-type interface. A main access emulator may emulate data storage processes responsive to commands of a command register of the ATA registers. A test controller may be operable to load a queue with predetermined error functions to be emulated by the tester. The queue may release error functions of the queue for emulation responsive to data of at least one of the command register and the emulator.
REFERENCES:
patent: 2004/0039969 (2004-02-01), Pratt et al.
Magnusson, P., Werner, B.; Efficient memory simulation in SimICS; Swedish Inst. of Comput. Sci., Kista, Sweden; This paper appears in: Simulation Symposium, 1995. Proceedings of the 28th Annual; Apr. 9-13, 1995; pp. 62-73□□.
IVP Generator; IBM Technical Disclosure Bulletin, Mar 1. 1991, vol. 33, Issue No. 10A, pp. 314-315.
ATA/ATAPI-6, Draft Specification Revision 3a Dec. 14, 2001 (provided on CD ROM).
Cypress Semiconductor Corporation
Dildine R. Stephen
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