Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-01-25
2011-01-25
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S042000, C714S045000
Reexamination Certificate
active
07877649
ABSTRACT:
An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.
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Eggers Georg
Hass Hermann
Kliewer Joerg
Proell Manfred
Ruf Wolfgang
Patterson & Sheridan LLP
Qimonda AG
Ton David
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