Method and apparatus for testing a high speed data receiver...

Details Method and apparatus for testing a high speed data receiver... Method and apparatus for testing a high speed data receiver...

2006-01-10

2006-01-10

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S700000, C713S500000

Reexamination Certificate

active

06986091

ABSTRACT:
A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a result, the jitter tolerance of the device under test is measured.

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patent: 6374388 (2002-04-01), Hinch
patent: 6580538 (2003-06-01), Kartalopoulos
patent: 6693881 (2004-02-01), Huysmans et al.

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