Method and apparatus for testing a device in an electronic...

Details Method and apparatus for testing a device in an electronic... Method and apparatus for testing a device in an electronic...

2007-10-16

2007-10-16

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10421771

ABSTRACT:
A method and apparatus is disclosed for testing a reconfigurable logic block. Preferably, this invention is intended to be used with Field Programmable Gate Array. According to the invention, a test bus addressing unit and a test bus activation unit are used to perform a test on a logic block. Upon selection of a corresponding logic block, a test data is outputted on a test bus which enables a testing of the logic function.

REFERENCES:
patent: 6425100 (2002-07-01), Bhattacharya
Sundararajan et al., “Testing FPGA Devices Using JBITS”, 2001 MAPLD International Conference, Laurel, Maryland, Sep. 2001, 8 sheets.

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