Method and apparatus for testing a circuit module concurrently w

Details Method and apparatus for testing a circuit module concurrently w Method and apparatus for testing a circuit module concurrently w

1997-09-23

2000-06-13

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714 30, 714 37, G01R 3128, H05K 1000

Patent

active

060761776

ABSTRACT:
Testing of a multi-module data processing system (20) includes performing a functional test on a module (42, 44, 46, 48, 50, 54) concurrently with an erase operation of a non-volatile memory module (34, 36). Because the erase operation requires multiple clock cycles to complete, and little or no interaction with a tester, a set of test patterns may be run on one or more of the modules (42, 44, 46, 48, 50, 54) while the erase operation is being performed. Between each test pattern, a special reset signal is provided to a reset unit (39) of a system integration unit (38). The special reset signal resets the modules (42, 44, 46, 48, 50, 54), without affecting the erase operation of the flash memory module (34, 36), in order to perform each test of the modules (42, 44, 46, 48, 50, 54) from a known state. Concurrent testing in this manner reduces the time required to test a multi-module data processing system.

REFERENCES:
patent: 5025205 (1991-06-01), Mydill et al.
patent: 5432797 (1995-07-01), Takano
patent: 5581510 (1996-12-01), Furusho et al.
patent: 5615216 (1997-03-01), Saeki

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