Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1998-07-30
2001-07-10
Lee, Thomas (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C709S241000, C713S500000, C713S502000, C713S503000, C713S600000
Reexamination Certificate
active
06260152
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to synchronizing circuits, and in particular, to a digital circuit for synchronizing multiple signals in systems having multiple clock domains.
DESCRIPTION OF THE RELATED ART
In an electronic system, it is common to have various sections of synchronous logic circuits operating with different clocks. These clocks are often unsynchronized, meaning there is no predefined relationship between their phases and/or frequencies. Each area of a circuit operated according to a common clock, unsynchronized with others, is typically referred to as a clock domain within the circuit. It should be noted that higher frequency synchronous clock signals can be derived from the common clock and used within the same domain.
Often, it is necessary to pass data between different clock domains. This can result in a problem that is referred to as “metastability.” Metastability occurs when a data input to a clock edge-triggered logic element, such as a flip-flop or register, changes value contemporaneously with a clock transition. In this event, the output of the edge-triggered element oscillates for a finite period, during which its value is indeterminate. During this time, the output is considered “metastable.” Metastability results in a data errors and unreliable operation.
To overcome problems caused by metastability, it is well known in the art to double-buffer unsynchronized inputs. An example of a double-buffer
14
is shown in FIG.
1
. In
FIG. 1
, a prior art digital system
10
that includes a first circuit
12
operating in clock domain
1
, and a second circuit
13
, operating in clock domain
2
. The second circuit
13
is a synchronous logic circuit using a common clock (CLK). Unsynchronized data passing from the first circuit
12
is synchronized to CLK by the double-buffer
14
. The double-buffer
14
includes a first D-flip-flop
16
and a second D-flip-flop
18
. Each of the flip-flops
16
-
18
transfers data on a common triggering edge of CLK. In the double-buffer
14
, the output of the first flip-flop (Q
0
) can enter a metastable state following a triggering edge of CLK. However, it is well known that Q
0
typically stabilizes prior to a subsequent triggering edge of CLK. Thus, the output of the second flip-flop
18
(Q
1
) is a reliable representation of the unsynchronized data input from the first circuit
12
.
A drawback of the double buffering scheme shown in
FIG. 1
is that each incoming unsynchronized signal requires its own double-buffer. Consequently, in modern digital systems having a multiplicity of signals crossing clock domain boundaries, the logic resources required to implement a double-buffer for every unsynchronized input becomes burdensome. For instance, providing a double-buffer for every unsynchronized signal in a very large scale integrated (VLSI) circuit requires large amounts of silicon area. This leads to higher power consumption, as well as increased manufacturing costs and circuit failure rates.
U.S. Pat. No. 5,638,015 discloses two alternative synchronization circuits, each having a section that includes a sequence of three flip-flops for synchronizing incoming signals. In spite of their apparent simplicity, these circuits are beset with serious drawbacks that limit their usefulness. For instance, the first circuit (
FIG. 2
of the '015 patent), requires an input pulse having a one-clock period duration. In response to this input, the circuit generates only a level output. The second circuit (
FIG. 3
of the '015 patent) detects only positive edge transitions on an unsynchronized input. These functional limitations reduce the usefulness of the '015 circuits. For example, in many logic circuits, it is necessary to generate a single pulse for every transition, positive or negative, occurring on an unsynchronized input. Neither of the circuits disclosed in the '015 patent is capable of providing this function.
Accordingly, there is a need for an improvement in synchronizing digital signals, one which is responsive to both positive and negative input edges, and which also results in lower power consumption, manufacturing costs, and failure rates.
SUMMARY OF THE INVENTION
It is an advantage of the present invention to provide a method and apparatus that overcomes the limitations and drawbacks of known techniques for synchronizing signals in a digital system. The present invention accomplishes this by providing an improved synchronization technique that does not require a double-buffer for every unsynchronized data signal crossing clock domain boundaries.
According to one aspect of the present invention, there is provided a synchronization circuit that includes three flip-flops responsive to a common clock signal (CLK). The input to the first flip-flop represents the least significant bit (LSB) of a counter included within a first clock domain. The CLK signal originates from a second clock domain. The output of the first flip-flop is provided as input to the second flip-flop, while the second flip-flop output is provided as input to the third flip-flop and an exclusive OR (XOR) gate. In response to outputs from the second and third flip-flops, the XOR-gate produces a synchronization signal for use within the second clock domain. The synchronization signal is active for one period of CLK, subsequent to every transition occurring on the LSB input. The active state of the synchronization signal indicates that a predefined set of unsynchronized data inputs are stable and valid. In this manner, a single unsynchronized input signal, i.e., the LSB input, can be used to synchronize a plurality of data inputs. This eliminates the need for a double-buffer on every unsynchronized data input. The counter provides additional benefit because its multi-bit output, including the LSB, can be used to control circuitry in either clock domain.
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Baca Russell T.
Cole Steven R.
Lee Thomas
Nguyen Tanh
Siemens Information and Communication Networks Inc.
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