Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Patent
1998-06-04
2000-03-21
Palys, Joseph E.
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
714731, 375362, G06F 112
Patent
active
060414170
ABSTRACT:
The present invention provides a method and apparatus for receiving and synchronizing data transmitted to a host interface unit of a graphics memory system on the rising and falling edges of a strobe signal in accordance with an accelerated graphics port (AGP) specification. An inner loop synchronization component, which is comprised in the host interface unit of the graphics memory system, receives data transmitted to the host interface unit on the falling and rising edges of a strobe signal and synchronizes the data to a PCI clock signal. The inner loop synchronization component comprises a first data transfer unit, a second data transfer unit and a control unit. The first data transfer unit comprises logic configured to capture the data transmitted on the falling edge of the strobe signal and to delay the captured data a predetermined number of cycles of the PCI clock before outputting the captured data from the first data transfer unit. The control unit detects the falling edge of the strobe signal and generates one or more timing signals based on the strobe signal. The rising edge of the strobe signal may or may not occur within the PCI clock cycle in which the falling edge of the strobe signal occurs. The second data transfer unit receives the timing signals generated by the control unit and utilizes the timing signals to capture the data transmitted on the rising edge of the strobe signal. The second data transfer unit then delays the captured data a predetermined number of cycles of the PCI clock before outputting the captured data from the second data transfer unit. The timing signals generated by the control unit are utilized by the second data transfer unit to ensure that the data transmitted on the rising edge of the strobe signal is output from the second data transfer unit in the same cycle of the PCI clock in which the data transmitted on the falling edge of the strobe signal is output from the first transfer unit.
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Dewey James M.
Hammond Maynard D.
Hewlett--Packard Company
Mai Rijue
Palys Joseph E.
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