Method and apparatus for supporting vector operations on a...

Details Method and apparatus for supporting vector operations on a... Method and apparatus for supporting vector operations on a...

2005-12-19

2009-12-08

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C712S209000, C703S026000

Reexamination Certificate

active

07631171

ABSTRACT:
One embodiment of the present invention provides a system that supports vector operations on a multi-threaded microprocessor. During operation, the system detects a vector instruction in a program. The system maps this vector instruction onto the thread contexts of the multi-threaded microprocessor. As part of the mapping process, the system splits the vector instruction across a set of threads that execute in parallel and generates a set of instructions for the set of threads. This mapping process allows the vector instruction to be executed efficiently across multiple threads.

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Hironaka, T., Hashimoto, T., Okazaki, K., Murakami, K., and Tomita, S. 1992. Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. In Proceedings of the 6th international Conference on Supercomputing (Washington D. C., Jul. 19-24, 1992). ICS '92. ACM Press, New York, NY, 272-281.
Andrew S. Tanenbaum; Structured Computer Organization; Second Edition; 1984; Section 1.4 (pp. 10-12).

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