Method and apparatus for supplying a clock to a device under...

Details Method and apparatus for supplying a clock to a device under... Method and apparatus for supplying a clock to a device under...

2008-12-15

2010-12-14

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C326S047000, C326S093000

Reexamination Certificate

active

07852109

ABSTRACT:
A method and apparatus involves operating a circuit having a test circuit interrupt input terminal (INTERRUPT), having a test circuit clock output terminal (DUT_CLK), and having first and second operational modes. In the first operational mode the circuit supplies a test circuit clock signal to the test circuit clock output terminal. The circuit responds to receipt of an occurrence of a test circuit interrupt at the test circuit interrupt input terminal by then operating in the second operational mode. In the second operational mode the circuit refrains from supplying the test circuit clock signal to the test circuit clock output terminal.

REFERENCES:
patent: 2004/0215442 (2004-10-01), Musselman
patent: 2008/0312900 (2008-12-01), Akiba et al.
System Generator for DSP, Release 10.1, Mar. 2008, Chapter 3, entitled “Using Hardware Co-Simulation”, pp. 175-188, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.

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