Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-04
2003-05-13
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S036000
Reexamination Certificate
active
06564348
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an improved data processing system and, in particular, to a method and system for data processing system reliability, and more specifically, for digital logic testing.
2. Description of Related Art
As computers become more sophisticated, diagnostic and repair processes have become more complicated and require more time to complete. A service engineer may “chase” errors through lengthy diagnostic procedures in an attempt to locate one or more components that may be causing errors within the computer. For example, a diagnostic procedure may indicate an installed component or field replaceable unit (FRU) that is a likely candidate for the error, and the installed FRU may be replaced with a new FRU. The reported problem may be considered resolved at that point. If, after further testing of the previously installed FRU, the FRU is later determined to be reliable, the original problem has not actually been resolved and may remain unresolved until the next error is reported. In addition to paying for unnecessary components, a business must also pay for the recurring labor costs of the service engineer and lost productivity of the user of the error-prone system.
Diagnosing errors during initial program load (IPL) is especially difficult because the operating system, which may contain sophisticated error logging functions, has not yet been loaded at that stage of system initialization, and the IPL code is purposefully devoid of many diagnostic functions in order to keep the IPL code efficient. Many computer systems employ chipsets designed with built-in self-tests (BISTs). The BISTs are dedicated test circuits integrated with other circuitry on a chip. During power-on reset (POR) of the system, POR BISTs automatically start and complete within a few seconds. As a result, a bit signature, or binary data pattern, is generated by the BIST. The IPL code reads the POR BIST signatures and compares the generated BIST signatures with predetermined signatures stored in the IPL code during code compilation, i.e. hardcoded into the IPL code. In addition to the POR BIST, the IPL code may initiate logical BISTs (LBISTs) or array BISTs (ABISTs) and verify their signatures.
A problem may arise when there is a need to update one of the system chipsets with a newer version. When a new chipset is deployed, any IPL code containing associated BIST signatures must be updated to reflect the BIST signatures for the new chips. For most systems, the IPL code is stored in a flash module on the native I/O (NIO) planar. If there is a problem during the flash update of the IPL code that corrupts the IPL code, then the NIO planar must be replaced. If the chipset that needs to be upgraded or parts of the chipset that become defective are on different planars then the NIO planar is on a different planar than the NIO planar, then multiple planars may be replaced. In either case, replacement of a flash module results in increased costs and downtimes.
Therefore, it would be advantageous to provide a method and apparatus for efficiently storing BIST signatures within a data processing system other than in the IPL module.
SUMMARY OF THE INVENTION
A method and apparatus for storing and using chipset built-in self-test (BIST) signatures is provided. A BIST for a chip in a data processing system may be initiated by a power-on-reset in the data processing system. The BIST signature generated during the BIST is compared with a predetermined BIST signature stored in a vital products data (VPD) module associated with the chip is read. A difference between the generated BIST signature and the predetermined BIST signature is then reported.
REFERENCES:
patent: 5557558 (1996-09-01), Daito
patent: 5638382 (1997-06-01), Krick et al.
patent: 5668947 (1997-09-01), Batcher
patent: 6104304 (2000-08-01), Clark et al.
Barenys Michael Anton
Goodwin Joel Gerald
Lim Michael Youhour
Mehta Chetan
International Business Machines - Corporation
McBurney Mark E.
Tu Christine T.
Yee Duke W.
Yociss Lisa L.B.
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