Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
1999-04-27
2001-10-30
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
Reexamination Certificate
active
06311285
ABSTRACT:
BACKGROUND
1. Field of the Disclosure
The present disclosure pertains to the field of signal transfer between components. More particularly, the present disclosure pertains to source synchronous transmission of signals at various frequency ratios with respect to a core frequency.
2. Description of Related Art
One limitation on throughput of processing in a computer or other processing system is the interconnection between integrated circuits and/or other components in the system. Interconnection circuits also typically consume significant amounts of power and space on the components. Improved interconnect techniques may advantageously allow faster signaling between components thereby increasing system throughput. Improved interconnect techniques may also allow different signaling levels that may either allow faster signaling or may reduce area or power consumption of the signaling circuits.
In some cases, interconnect circuits are unable to transfer data as rapidly as a component produces or requests data. One prior art mechanism for dealing with this problem is to provide a bus interface that operates at a lower frequency than a core portion of the component. For example, a number of Intel Pentium® Processors have a core frequency that operates at either even fractional multiplier (e.g., a 1:2, 1:3, etc., bus to core frequency ratio) or an odd fractional multiplier (e.g., a 2:3, 2:5, etc., bus to core frequency ratio).
These processors, however, generally do not employ a source synchronous scheme to interface with a general system bus. The interface with the system bus is referred to as a front side bus as some processors employ a back side bus to interface with a cache memory. The front side bus typically employs a clocking scheme where signals are latched and captured with reference to a common system clock signal rather than one which is transferred along with the data or command signals being transferred as is done in a typical source synchronous arrangement.
Prior art processors also include back side buses employing source synchronous signaling. In fact such source synchronous signaling has been accomplished using even fractions of the core clock frequency in processors such as the Intel Pentium® II processor. Prior art processors, however, may not have implemented an adequate source synchronous interface for high speed operation at a bus frequency that is an odd fraction of the core clock frequency.
SUMMARY
A method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency is disclosed. A disclosed apparatus includes a signal driver circuit and a strobe signal driver circuit. The signal driver circuit is coupled to generate a cycle for a first signal at a first frequency from a core signal from a core operating at a core clock frequency that is an odd fractional multiple of the first frequency. The strobe signal driver circuit is coupled to generate a strobe signal at an intermediate point of the cycle to allow latching of the first signal triggered by the strobe signal.
REFERENCES:
patent: 5754833 (1998-05-01), Singh et al.
patent: 5781765 (1998-07-01), Alexander
patent: 5802132 (1998-09-01), Pathikonda et al.
patent: 5915107 (1999-06-01), Maley et al.
patent: 6145100 (2000-11-01), Madduri
patent: WO 99/15980 (1999-04-01), None
Douglas Kenneth R.
Llkbahar Alper
Muljono Harry
Rodriguez Pablo M.
Draeger Jeffrey S.
Heckler Thomas M.
Intel Corporation
LandOfFree
Method and apparatus for source synchronous transfers at... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for source synchronous transfers at..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for source synchronous transfers at... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2595886