Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-07-28
2008-08-19
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07415645
ABSTRACT:
A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system.
REFERENCES:
patent: 5031180 (1991-07-01), Mciver et al.
patent: 5307142 (1994-04-01), Corbett et al.
patent: 6028983 (2000-02-01), Jaber
patent: 6127864 (2000-10-01), Mavis et al.
patent: 6304122 (2001-10-01), Gregor et al.
patent: 6504410 (2003-01-01), Waldie et al.
patent: 6504411 (2003-01-01), Cartagena
patent: 2001/0038304 (2001-11-01), Waldie et al.
patent: 2002/0095641 (2002-07-01), Cartagena
patent: 2004/0227551 (2004-11-01), Gardner
Drake Alan J.
Martin Andrew K.
Osowski AJ Klein
International Business Machines - Corporation
Kerveros James C
Musgrove Jack V.
Salys Casimer K.
LandOfFree
Method and apparatus for soft-error immune and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for soft-error immune and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for soft-error immune and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3994214