Method and apparatus for sequencing system bus grants and disabl

Details Method and apparatus for sequencing system bus grants and disabl Method and apparatus for sequencing system bus grants and disabl

1996-05-10

2000-02-15

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710128, G04F 1300

Patent

active

060264608

ABSTRACT:
A method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge includes a bus activity monitor for monitoring bus cycles on a first bus, an inbound posting buffer, and a control logic. The control logic indicates whether to grant control of the first bus to a first processor on the first bus based on whether the inbound posting buffer is empty, and also controls disabling of posting to the inbound posting buffer. The control logic disables inbound posting responsive to both the first processor being backed off the system bus a predetermined number of times and the inbound posting buffer being empty.

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