Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-02-19
2000-05-30
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714733, 365201, 36523005, G11C 2900, G01R 3128
Patent
active
060702567
ABSTRACT:
A method for and apparatus of testing a multi-port RAM (random access memory) detect single port faults and inter port shorts in multi-port random access memories. The algorithm performs a conventional single-port test such as MARCH or SMARCH on one port of the memory and performs an inter-port test on all other ports. The algorithm does not impose any extra test time and requires the addition of only a few gates to a conventional single-port BIST controller, independently of the size of the memory. An address to select ports of the multi-port RAM includes a row address signal of a plurality of bits. A specific bit of the row address signal is changed.
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Gupta Sanjay
Wu Yuejian
de Wilton Angela C.
Moise Emmanuel L.
Nortel Networks Corporation
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