Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-03-16
1997-07-08
Hudspeth, David R.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 98, 327141, H03K 19096
Patent
active
056465548
ABSTRACT:
The invention relates to the design and operation of local clock control circuits which operate to supply a local clock signal to a controlled block of a digital circuit in response to an enable signal representative of an enable condition. The invention is embodied in several alternative local clock control circuits which comprise a signal joining means or a signal joining means in combination with an enable signal relay means. The signal joining characteristics of the Muller C-element are used advantageously in several embodiments. The invention serves to ease constraints on the arrival time of an enable signal at the local clock control circuit.
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Kim Seokjin
Sridhar Ramalingam
Hudspeth David R.
Research Foundation of State University of New York
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