Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-10-09
2002-10-15
Wong, Peter (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S724000, C714S738000, C709S241000
Reexamination Certificate
active
06467051
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
A number of related copending United States patent applications commonly owned by the assignee of the present document and incorporated by reference in their entirety into this document are being filed in the United States Patent and Trademark Office on or about Oct. 9, 1998. The list of these applications is as follows: Ser. No. 09/169,320, entitled “METHOD AND APPARATUS FOR LIMITED ACCESS CIRCUIT TEST”; Ser. No. 09/169,597, entitled “METHOD AND APPARATUS FOR SELECTING STIMULUS LOCATIONS DURING LIMITED ACCESS CIRCUIT TEST”; Ser. No. 09/169,777, entitled “METHOD AND APPARATUS FOR SELECTING TARGETED COMPONENTS IN LIMITED ACCESS TEST”; Ser. No. 09/169,710, entitled “METHOD AND APPARATUS FOR CANCELING ERRORS INDUCED BY THE MEASUREMENT SYSTEM DURING CIRCUIT TEST”; Ser. No. 09/169,709, entitled “METHOD AND APPARATUS FOR CORRECTING FOR DETECTOR INACCURACIES IN LIMITED ACCESS TESTING”; and, Ser. No. 09/169,502, entitled “METHOD AND APPARATUS FOR BOARD MODEL CORRECTION.”
FIELD OF THE INVENTION
This invention relates generally to circuit board testing. More particularly, this invention relates to the identification of manufacturing defects and faulty components on a circuit board.
BACKGROUND OF THE INVENTION
Generally, a circuit board consists of numerous interconnected components such as semiconductor chips, resistors, capacitors, inductors, etc. After circuit boards have been assembled, but before they can be used or placed into assembled products, they must be tested. Testing verifies that the proper components have been used, that each component performs within test limits, that all required electrical connections have been properly completed, and that all necessary electrical components have been attached to the board in the proper position and with the proper orientation. When a component is not performing within test limits, it is said to be faulty.
A common way to test assembled printed circuit boards is called in-circuit test. In-circuit testing involves probing individual board components through a so-called “bed-of-nails” and verifying their existence and specifications independent of surrounding circuitry. A well known series of circuit board testing machines for in-circuit testing is the Hewlett-Packard Company Model HP-3070 Family of Circuit Board Testers. The HP-3070 Family of board testers are fully described in the HP-3070 Family Operating and Service Manuals available from Hewlett-Packard Company. Other families of circuit board testing machines made by Hewlett-Packard are the HP-3060 and HP-3065 series.
To test each individual board component, in-circuit testing requires access to every node on the circuit board. With through-hole parts, access is directly available at component leads. With surface mount parts, access is provided through vias and test pads that are placed on the circuit board when it is designed. Increases in board density, however, have led to a decrease in the size of vias that has eclipsed the ability of probe technology to contact a smaller target. Vias now are often one hundred times smaller in area than vias used just a few years ago. Furthermore, test pads that are large enough to be probed successfully require a substantial amount of board area that would otherwise be used to place and connect components. Therefore, on many circuit boards it is no longer practical, or desirable, to probe every node on the board.
Accordingly, there is a need in the art for a test technique and apparatus that can test individual circuit board components having tolerances without requiring access to every node on the circuit board. Such a technique should be generalized so that it can be used with many different circuits and tolerance ranges. Furthermore, it is desirable that such a system be implemented on existing in-circuit testing hardware to preserve existing capital and process investments in that hardware.
SUMMARY OF THE INVENTION
In a preferred embodiment, the invention selects accessible nodes from a larger group of accessible nodes as test points to test a selected group of components that contain at least one inaccessible node. By selecting a subset of the larger group of accessible nodes, the complexity of the test problem is reduced. Also, the number of measurements, and time, necessary to test the selected group of components is reduced. The invention is generally applicable to all kinds of circuits and may be implemented using existing computer and tester hardware.
After the components are selected for testing, they are arranged into equivalence classes using all of the available accessible nodes. Accessible nodes that are not directly connected to the components being tested are removed one by one as accessible nodes to see if the equivalence classes change. If the equivalence classes change, the node is restored as an accessible node since it is necessary as a test point for the selected group of components. If the equivalence classes do not change, then the node is not necessary as a test point for the selected group of components. This process eliminates unnecessary nodes as test points so the remaining nodes are the test points for the selected group of components.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5172377 (1992-12-01), Robinson et al.
patent: 5323108 (1994-06-01), Marker, III et al.
patent: 5510704 (1996-04-01), Parker et al.
patent: 5513188 (1996-04-01), Parket et al.
patent: 5627842 (1997-05-01), Brown et al.
patent: 5808919 (1998-09-01), Preist et al.
Jri Vlach and Kishore Singhal, “Computer Methods For Circuit Analysis and Design,” Van Nostrand Reinhold Publishing, New York, NY, 1983, Chapter 4, “General Fornulation Methods,” pp. 100-151, Chapter 5, “Sensitivities.” pp. 152-170.
Leon O. Chua and Pen-Min Lin, “Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques,”, Prentice-Hall, 1975, Chapter 4, “Nodal Linear Network Analysis: Algorithms and Computational Methods,” pp. 166-203, Chapter 17, Advanced Algorithms and Computational Techniques for Computer Simulation Programs, pp. 665-717.
Yoshio Togawa, Takashi Matsumoto, & Hideki Arai, “The Tf-Equivalence Class Approach to Analog Fault Diagnosis Problems”, IEEE Transactions on Circuits and Systems, vol. CAS-33, No. 10, Oct. 1986, pp. 992-1009.
Jiri Vlach and Kishore Singhal, Computer Methods for Circuit Analysis and Design, Van Nostrand Reinhold Publishing, New York, NY, 1983.
Leon O. Chau & Pen-Min Lin, Computer Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques, Prentis Hall, 1975.
Gary D. Hactel, Robert K. Brayton, and Fred G. Gustavson, “The Sparse Tableu Approach to Network Analysis and Design” IEEE Transactions on Circuit Theory, vol. CT-18, No. 1, Jan. 1971, pp. 101-113.
Kenneth P. Parker, John e. McDermid and Stig Oresjo “Structure and Metrology for an Analog Testability Bus” Proceeding of the IEEE International Test Conference, Baltimore, Maryland, Oct. 1993, pp. 309-322.
Juin-Lang Huang & Kwang-Ting Cheng “Analog Fault Diagnosis for Unpowered Circuit Boards” Proceedings of the IEEE International Test Conference, Washington, DC, Nov. 1997, pp. 640-648.
John McDermid “Limited Access Testing: IEEE 1149.4 Instrumentation & Method”, Proceeding of the IEEE International Test Conference, Oct. 1998, pp. 388-395.
John McDermid, “Limited Access Testing: Ability and Requirements” Proceedings of the Technical Program. NEPCON West '98, Mar. 1998, vol. 2, pp. 736-742.
R. Lui, Testing and Diagnosis of Analog Circuits and Systems, Van Nostrand & Reihold, NY, 1991.
S.D. Bedrosian, “On Element Value Solution of Single-Element-Kind Networks”, Ph. D. Dissertation, University of Pennsylvania, Dec. 1961.
Timothy N. Trick, Wataru Mayeda, and Adel A. Sakla, “Calculation of Parameter Values from Node Voltage Measurements”, IEEE Transactions on Circuits and Systems, vol. CAS-26, No.
Ahrikencheikh Cherif
Browen Rodney A.
Darbie William P.
Lannen Kay C.
McDermid John E.
Agilent Technologie,s Inc.
Neudeck Alexander J.
Phan Raymond N
Wong Peter
LandOfFree
Method and apparatus for selecting test point nodes of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for selecting test point nodes of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for selecting test point nodes of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2992104