Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-12-22
2004-06-15
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S500000, C713S501000, C713S503000, C331S018000, C331S025000, C375S359000, C375S362000, C375S371000
Reexamination Certificate
active
06751743
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of clock synchronization and more particularly to the flexible synchronization of several clocks of different frequencies across process, voltage and temperature (PVT) variations and other timing differences between devices.
2. Description of the Related Art
A data communications network is the interconnection of two or more communicating entities (i.e., data sources and/or sinks) over one or more data links. A data communications network allows communication between multiple communicating entities over one or more data communications links. High bandwidth applications supported by these networks include streaming video, streaming audio, and large aggregations of voice traffic. In the future, the demands for high bandwidth communications are certain to increase. To meet such demands, an increasingly popular alternative is the use of lightwave communications carried over fiber optic cables. The use of lightwave communications provides several benefits, including high bandwidth, ease of installation, and capacity for future growth.
The synchronous optical network (SONET) protocol is among several protocols designed to employ an optical infrastructure. SONET is widely employed in voice and data communications networks. SONET is a physical transmission vehicle capable of transmission speeds in the multi-gigabit range, and is defined by a set of electrical as well as optical standards. A similar standard to SONET is the Synchronous Digital Hierarchy (SDH) which is the optical fiber standard predominantly used in Europe. There are only minor differences between the two standards. Accordingly, hereinafter any reference to the term SONET refers to both SDH and SONET networks, unless otherwise noted.
SONET utilizes a byte-interleaved multiplexing scheme. Multiplexing enables one physical medium to carry multiple signals. Byte-interleaving simplifies multiplexing and offers end-to-end network management. Each STS is transmitted on a link at regular time intervals (for example, 125 microseconds) and grouped into frames. See Bellcore Generic Requirements document GR-253-CORE (Issue 2 Dec. 1995), hereinafter referred to as “SONET Specification,” and incorporated herein by reference for all purposes. The first step in the SONET multiplexing process involves the generation of the lowest level or base signal. In SONET, this base signal is referred to as synchronous transport signal—level 1, or simply STS-1, which operates at 51.84 Mbps (Megabits per second). Data between adjacent nodes is transmitted in these STS modules. Higher-level signals are integer multiples of STS-1, creating the family of STS-N signals in Table 1. An STS-N signal is composed of N byte-interleaved STS-1signals. Table 1 also includes the optical counterpart for each STS-N signal, designated optical carrier level N (OC-N).
TABLE 1
SIGNAL
BIT RATE (Mbps)
STS-1, OC-1
51.840
STS-3, OC-3
155.520
STS-12, OC-12
622.080
STS-48, OC-48
2,488.320
STS-192, OC-192
9,953.280
NOTE:
Mbps = Megabits per second
STS = synchronous transport signal
OC = optical carrier
SONET organizes STS data streams into frames, consisting of transport overhead and a synchronous payload envelope. The overhead consists of information that allows the network to operate and allow communications between a network controller and nodes. The transport overhead includes framing information and pointers, and performance monitoring, communications, and maintenance information. The synchronous payload envelope is the data to be transported throughout the network, from node to node until the data reaches its destination.
In a system transferring STS-192 data streams at 9.953280 Gbps (Giga bits per second), it is impractical to clock all devices at that high rate. In digital transmission, a clock refers to a series of repetitive pulses that keep the bit rate of data constant and indicate the location of ones and zeroes in a data stream. Instead of clocking all devices at the high data stream rate, data is often transferred between devices at lower data rates, then increased to the higher data rate. For example, a serial bit stream operating at a high data rate can be de-serialized into 16 parallel bits and clocked at {fraction (1/16)}
th
the high data rate and later serialized again running at the higher data rate without changing the amount of data throughput. A framing logic device manipulates the data stream at clock rates ranging from 38.88 MHz to 622.08 MHz. The framing logic device (also referred to as a “framer”) transmits a 16-bit parallel data stream to a serializer at 622.08 MHz. The serializer sends the parallel data stream as a bit wide data stream at 9.953280 GHz.
With every increase in SONET data rates, from OC-3 to OC-12 to OC-48 to OC-192, timing problems are introduced between the framer and the serializer. Timing mismatches between devices can occur due to different integrated circuit (IC) technologies. SONET framers tend to be designed in high density, low speed technologies such as CMOS, while SONET serializers tend to be designed in low density, high speed technologies such as Silicon BiPolar or Gallium Arsenide (GaAs). This mismatch in technologies creates disparate data setup and hold times that must be resolved between devices. Furthermore, as SONET data rates increase higher, the amount of timing skew due to process, voltage and temperature variations (PVT) in CMOS processes can exceed a full clock cycle. Additional circuitry is needed to ensure that the transfer of the data stream between the framer and the serializer is kept synchronous.
FIG. 1
illustrates a prior art circuit for synchronizing two clocks using PLL circuitry. A reference clock, labeled CLK A, and an oscillator clock, labeled CLK B, are fed into a phase detector
110
that detects the phase difference between the two clocks. The phase difference output is sent through a low pass filter
120
and an amplifier
130
and controls the frequency of a voltage controlled oscillator (VCO)
140
. The phase difference output that is generated by phase detector
110
is used to retune the frequency of VCO
140
whenever CLK B deviates from CLK A. In this way, the frequency of VCO
140
is driven toward the frequency of reference clock CLK A. CLK B tracks the phase of CLK A and locks to CLK A through the feed back loop.
Simply synchronizing two clocks, for example, synchronizing a 622.08 MHz clock which is received by the serializer to a 622.08 MHz clock which is received by the framer, does not take into account any timing differences, such as PVT variations, through the devices. Adding additional circuitry to either the framer or serializer is not desirable due to the low speed technology used for the framer and the low-density technology used for the serializer. A clock synchronizing circuit is needed that is easy to implement on a printed circuit (PC) board, requires no additional support circuitry in either the serializer or the framer, and accounts for PVT variations and other timing differences between the framer and the serializer.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and apparatus for synchronizing clocks is provided that is flexible and compensates for PVT variations and other timing differences between two devices. The method includes producing an up-converted clock from a system clock, the up-converted clock having a frequency that is a multiple of the frequency of the system clock, producing an aligned clock from a data-aligned clock from a first device and a counter clock from a second device, producing a de-jittered clock, selecting a first reference clock to send to the first device from the up-converted clock, the aligned clock and the de-jittered clock, and selecting a second reference clock to send to the second device from the up-converted clock, the aligned clock and the de-jittered clock.
Another embodiment of the invention is directed to an apparatus which includes a system PLL circuit for producing an up
Heston Matthew L.
Theodoras, II James T.
Campbell Stephenson Ascolese LLP
Cisco Technology Inc.
Lee Thomas
Trujillo James K
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