Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-06-04
2011-11-01
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
08051345
ABSTRACT:
The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.
REFERENCES:
patent: 5357572 (1994-10-01), Bianco et al.
patent: 5826007 (1998-10-01), Sakaki et al.
patent: 6578180 (2003-06-01), Tanner
patent: 7062659 (2006-06-01), Bae
patent: 7490231 (2009-02-01), Turner et al.
patent: 2003/0204801 (2003-10-01), Tkacik et al.
patent: 2008/0010570 (2008-01-01), Yamazaki
patent: 2009/0307502 (2009-12-01), GadelRab et al.
PCT International Searching Authority, International Search Report for PCT Application No. PCT/US2009/046094, Sep. 10, 2009.
Hely, D.; Bancel, F.; Flottes, M.; Rouzeyre, B.: “Test Control for Secure Scan Designs”, Test Symposium, 2005, European Tallinn, Estonia, May 22-25, 2005, Piscataway, NJ, USA, IEEE, May 22, 2005, pp. 190-195, XP010801332, ISBN: 978-0-7695-2341-5, Chapter 3.
Du Bin
Foley Denis
GadelRab Serag M.
Syed Zeeshan S.
ATI Technologies ULC
Gaffin Jeffrey A
McMahon Daniel F
Vedder Price P.C.
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