Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-09-07
2003-11-25
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06654917
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an improved chip organization and, in particular, to a method and apparatus for scanning free-running logic. Still more particularly, the present invention provides a method and apparatus for scanning free-running logic that controls system pervasive functions while maintaining the state of the system that the free-running logic controls.
2. Description of Related Art
Prior art chip designs use macros to control the clocks to the chip plus provide the interface to an external service processor. These macros source the control for a scan function of the chip logic, and supply other pervasive control functions, such as built-in-self-test, off-chip-driver enable control, and boundary scan control. Scanning is a method for testing chips on a printed circuit board by building the chip with additional input and output pins that are only used for test purposes. Full scan methods test all the registers on the chip. Partial scan tests some of them, and boundary scan tests only the input/output cells.
With reference to
FIG. 1
, a block diagram is shown depicting a prior art processor chip with pervasive control functions. The chip
100
includes a logic function portion
101
and a test and diagnostics portion
102
. The chip communicates with a service processor
130
through a joint test action group (JTAG) bus
140
. JTAG is the Institute of Electrical and Electronics Engineers (IEEE) standard for boundary scan.
The logic function portion includes logic units
104
,
106
and scan switch
108
. For simplicity, the example in
FIG. 1
shows only two logic units; however, logic function portion
101
typically includes many more logic units. The test and diagnostics portion includes test and diagnostics control logic
110
, asynchronous interface logic
112
, and a JTAG test clock (TCK) clock partition
114
. The JTAG TCK partition includes data registers
116
, instruction register
118
, input/output (I/O)
120
, and state machine
122
. The test and diagnostics control logic is also referred to as the “free-running logic.”
The term “logic unit” refers to a grouping of similar logic functions. Such a grouping of functions may also be referred to as a “cluster.” For purposes of discussion, the test and diagnostic control logic is also referred to as a logic unit, namely the “free-running logic unit.” The term “free-running” refers to the fact that the test and diagnostics control logic has clocks which conventionally never stop, because the logic controls the operation of the chip to do scanning when the clocks to the other logic units are stopped.
Test and diagnostics control logic
110
controls the scanning of logic units in the logic function portion through control interface
124
. The service processor
130
receives test data input and test output through I/O
120
. The service processor provides test clock through TCK and advances through states in state machine
122
through TMS. Test and diagnostics control logic
110
and logic units
104
,
106
operate under a high-speed mesh clock (mclk). Asynchronous interface logic
112
provides an interface between the high-speed free-running logic and the slower test clock.
According to the 1149.1 IEEE JTAG specifications, instructions are loaded into instruction register
118
through the JTAG bus. TDI input serially shifts into an instruction-shift register based on the JTAG state machine, which itself is under the control of the JTAG TMS/TCK pins. When an instruction to scan a logic unit is in instruction register
118
, the instruction is decoded to assert the appropriate scan select signal. The number “n” of scan select signal lines is equal to the number of logic units in logic function portion
101
. The scan select signals are then used in scan switch
108
to forward the appropriate I/O signal from the logic units to I/O
120
. The scan select signal is also used to select the appropriate logic unit for a write to a register through test data in (TDI).
A disadvantage of the prior art is that the test and diagnostics control logic is not itself scannable and so it lacks the very same system scan support that it provides to the functional units, such as an instruction unit, on the chip. The fact that the macros, which control the broad sweeping functions on the chip, like clocking, do not themselves support scanning and the setting of latches via scan presents a problem concerning usability of initial hardware if a circuit, mask, or logic problem ever manifests. As chips become more complex and the speeds of chips surpass the one gigaherz range, the ability of the test and diagnostics control logic to function properly is of increasing importance.
Thus, it would be advantageous to provide a method and apparatus for scanning the free-running logic in the test and diagnostics portion of a chip.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for scanning the test and diagnostics control logic on a chip. The state of the chip logic is maintained in a frozen state as a scan of the normally free-running logic occurs. The chip is configured to select the test and diagnostics control logic if an instruction to scan the test and free-running logic is in the instruction register. A scan switch is configured to pass the scan output from the free-running logic to the test data output on the chip. Test data input is passed to the test and diagnostics control logic through the use of the scan select, as with the other logic units. The control interface is configured to feed a stop control and scan control signal back to the free-running logic under control of stop enable and scan enable signals. Outputs are forced to an electrically safe value by shadowing the driver control register, which controls the functional output.
REFERENCES:
patent: 5812562 (1998-09-01), Baeg
patent: 6018815 (2000-01-01), Baeg
patent: 6260166 (2001-07-01), Bhavsar et al.
Floyd Michael Stephen
Reick Kevin F.
Skergan Timothy M.
Chase Shelly A
De'cady Albert
Salys Casimer K.
Tkacs Stephen R.
Yee Duke W.
LandOfFree
Method and apparatus for scanning free-running logic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for scanning free-running logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for scanning free-running logic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3183963