Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-11-26
1999-11-02
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714733, G01R 3128
Patent
active
059789441
ABSTRACT:
A method and apparatus comprising a first circuit configured to receive a mode signal and generate a first signal and a second signal, the first circuit being configured to deassert the first signal and the second signal when the mode signal is in a first state; a first scan cell configured to latch a first input in response to the first signal and to latch a second input in response to a third signal to produce a first latched signal on a first output, the first scan cell configured to drive a second output in response to a fourth signal, wherein the second input and the second output are coupled to a scan chain; a dynamic circuit having a dynamic node, the dynamic circuit being configured to receive the first output and the second signal, to precharge the dynamic node in response to the second signal being deasserted, and produce a data on the third output in response to the second signal being asserted and the state of the dynamic node; and a second cell configured to latch the data in response to the second signal being deasserted.
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PCT Search Report, International Application No.: PCT/US98/17948, mailed Nov. 9, 1998, 4pgs.
Gruner Fred
Parvathala Praveen
Beausoliel, Jr. Robert W.
Intel Corporation
Iqbal Nadeem
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