Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-04-16
2001-11-06
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S376000, C327S158000, C327S161000
Reexamination Certificate
active
06314149
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to improvements in methods and circuitry for rephasing a signal, and, more particularly, to improvements in methods and circuitry for rephasing an input signal based upon an error signal voltage, for use, for example, in rephasing a voltage controlled clock signal, or the like.
2. Relevant Background
Many circuits that depend upon or use clock signals have an adjustable delay circuit to delay the clock pulse by an adjustable amount. One such circuit includes an adjustable delay element that receives and delays the input signal to produce an output that is connected to a phase lock loop, which generates a clock signal. The clock signal is fed back to a multiplier that multiplies it by the input signal. The product is a phase error current signal, which is applied to the delay circuit to control the delay thereof. Thus, the phase of the clock is adjusted relative to the input signal to maintain a constant phase delay value.
This function is called clock rephasing. The result of this closed loop system achieves both a frequency and phase alignment of the signal and clock at the multiplier.
The previous delay methods used the error current directly to adjust a ramp current that is used to delay the input signal to achieve the desired phase of the output signal. However, using such techniques has several disadvantages. More specifically, the initialization of the delay circuit that is associated with such delay method involves fairly complicated analysis. In particular, the circuitry that may be associated with the overall delay circuitry may itself have numerous circuits that have inherent delay creating effects. In order to eliminate the effects of such delay creating circuits an overall rephasing circuit, for example, currents in the delay circuitry need to be determined. However, the overall delay is generally regarded as being inversely proportional to a sum of correcting currents. Moreover, each of the correcting currents may influence the delays that are associated with the various delay creating circuits. Thus, the cancellation of the delays can be an extremely complex problem.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an improved delay element for use in a clock rephasing system, or the like.
It is another object of the invention to provide an improved clock rephase system using the improved delay element.
It is another object of the invention to provide an improved clock rephase system of the type described, in which individual contributions of most propagation delays in the circuit can be compensated, without affecting each other.
These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read in conjunction with the accompanying drawings and appended claims.
Thus, according to a broad aspect of the invention, a pulse rephasing circuit for receiving an input signal and generating an output signal is presented. The circuit includes a circuit for generating a control voltage of magnitude related to a phase difference between the input and output signals. The circuit for generating a control voltage may be, for example, a multiplier circuit to which both the input and output signals are applied. A delay circuit receives the input signal to produce an output signal that has been delayed with respect to the input signal an amount related to the magnitude of the control voltage. The delay circuit may include a capacitor, a circuit for linearly charging the capacitor, a circuit for comparing the control voltage to a voltage charged on the capacitor, and a circuit for generating a state change in the output signal when the voltage charged on the capacitor exceeds the control voltage.
According to another broad aspect of the invention, a pulse rephasing circuit is provided that has a multiplier for receiving an input signal and a delay circuit for receiving the input signal to produce an output signal that has been delayed with respect to the input signal. A phase lock loop receives the output signal to produce a clock signal for application to another input of the multiplier circuit. An output of the multiplier circuit provides a control voltage to the delay circuit that is related in magnitude to a phase difference between the input signal and the clock signal, whereby the delay circuit is enabled to operate to delay the input signal an amount related to the magnitude of the control voltage.
According to yet another broad aspect of the invention, a method is presented for rephasing an input signal. The method includes the acts of producing an output signal based upon and having the same frequency as the input signal, generating a voltage of magnitude related to a phase difference between the input and output signals, and delaying the input signal an amount related to the magnitude of the control voltage prior to the act of producing an output signal.
According to still another broad aspect of the invention, a delay circuit is presented for delaying an input signal an amount depending upon a control voltage. The delay circuit has a capacitor and a circuit for linearly charging a voltage onto the capacitor. A switch is controlled by the input signal to connect the circuit for linearly charging the capacitor to the capacitor. A comparator generates an output signal, and a circuit is provided for generating a voltage proportional to a phase difference between the input signal and the output signal. The comparator is connected to compare the voltage charged on the capacitor with the voltage proportional to a phase difference between the input signal and the output signal to provide the output signal when the voltage charged on the capacitor becomes larger than the voltage proportional to a phase difference between the input signal and the output signal.
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Brady W. James
Chin Stephen
Ha Dac V.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
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