Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-05-23
2006-05-23
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07051255
ABSTRACT:
A method and apparatus for reducing power dissipation during a scan operation during testing of digital logic circuits which provides for scanning data while switching a limited number of nodes during scan-in and scan-out of input and result chains, and which isolates the logic circuit from random stimulation by scan chains as they are scanned. A scan chain includes a plurality of level sensitive scan design LSSD scan latches, each comprising a master latch M and a slave latch S. The master latch has a first input port D used for operation in a functional mode, and a second input port S used for operation in a scan mode, a scan enable input port, and a clock input port. The master latch M produces output scan data Sout which is directed to a slave latch S which produces a data output Q for the logic circuit under test.
REFERENCES:
patent: 5459735 (1995-10-01), Narimatsu
patent: 5719504 (1998-02-01), Yamada
patent: 6023778 (2000-02-01), Li
Ismet Bayraktaroglu, et al, (2001), Test Volume and Application Time Reduction Through Scan Chain Concealment, DAC, pp. 1-5.
Karra, Esq. Satheesh K.
Scully , Scott, Murphy & Presser, P.C.
Tu Christine T.
LandOfFree
Method and apparatus for reducing power dissipation in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for reducing power dissipation in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing power dissipation in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3559928