Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1996-07-25
1996-12-17
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326101, 327544, H03K 19096, H03K 1900
Patent
active
055857450
ABSTRACT:
An integrated circuit with power conservation includes a number of functional blocks, each of which includes digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks. The clock controller is operative to modulate the input clock in accordance with the signals on the clock control lines to provide modulated clocks to each of the plurality of functional blocks. A method for reducing power consumption includes the steps of: a) receiving control signals from a number of functional blocks; b) selectively deactivating a particular functional block upon a request from that functional block or from another functional block; and c) activating the particular functional block upon a request from another functional block.
REFERENCES:
patent: 5140184 (1992-08-01), Hamamoto et al.
patent: 5239215 (1993-08-01), Yamaguchi
patent: 5430397 (1995-07-01), Itoh et al.
Jayavant Rajeev
Simmons Laura E.
Santamauro Jon
VLSI Technology Inc.
Westin Edward P.
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