Laura E. Simmons

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Asynchronous latch circuit and register

Excavating
Patent

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Asynchronous latch circuit and register

Excavating
Patent

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Logic level shifter for 3 volt CMOS to 5 volt CMOS or TTL

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
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Method and apparatus for reducing power consumption in digital e

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
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Method and apparatus for reducing power consumption in digital e

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent

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Profile ID: LFUS-PAI-P-534487

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