Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-05-27
2008-08-05
Duncan, Marc (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S010000, C712S228000
Reexamination Certificate
active
07409589
ABSTRACT:
A method and apparatus are provided for reducing the number of cycles required to checkpoint instructions in a multi-threaded microprocessor that has dispatch group checkpointing. A determination is made in a first stage of a checkpoint pipeline whether checkpointing can occur for a group of instructions. The results of processing the group of instructions flow to a second stage of the checkpoint pipeline regardless of whether the group of instructions is ready to checkpoint. If the group of instructions is ready to checkpoint, the group of instructions is checkpointed in a third stage of the checkpoint pipeline.
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Mack Michael James
Ward Kenneth Lundy
Duncan Marc
Gerhardt Diana L.
International Business Machines - Corporation
Yee Duke W.
Yociss Lisa L. B.
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