Method and apparatus for reducing leakage power in a cache...

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C713S320000, C711S145000

Reexamination Certificate

active

07472302

ABSTRACT:
An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased. When a cache line is later accessed after being decayed, a cache miss is incurred and a test is performed to evaluate the cache decay performance by determining if the same cache contents are again accessed (e.g., whether the address associated with a subsequent access is the same address of the previously stored contents). The cache decay interval is then adjusted accordingly.

REFERENCES:
patent: 4420807 (1983-12-01), Nolta et al.
patent: 5430683 (1995-07-01), Hardin et al.
patent: 5632038 (1997-05-01), Fuller
patent: 5737746 (1998-04-01), Hardin et al.
patent: 5813022 (1998-09-01), Ramsey et al.
patent: 5813028 (1998-09-01), Agarwala et al.
patent: 5835435 (1998-11-01), Bogin et al.
patent: 5835949 (1998-11-01), Quattromani et al.
patent: 6041401 (2000-03-01), Ramsey et al.
patent: 6070232 (2000-05-01), Ishida et al.
patent: 6138213 (2000-10-01), McMinn
patent: 6141283 (2000-10-01), Bogin et al.
patent: 6157977 (2000-12-01), Sherlock et al.
patent: 6345336 (2002-02-01), Takahashi
patent: 6385697 (2002-05-01), Miyazaki
patent: 6408364 (2002-06-01), Tan et al.
patent: 6473814 (2002-10-01), Lyons et al.
patent: 6490654 (2002-12-01), Wickeraad et al.
patent: 6510494 (2003-01-01), Arimilli et al.
patent: 6535961 (2003-03-01), Wilkerson et al.
patent: 6795896 (2004-09-01), Hart et al.
Stefanos Kaxiras, Zhigang Hu, Girija Narlikar, Rae McLellan, “Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power”, First International Workshop on Power-Aware Computer Systems (PACS), Nov. 12, 2000.
Philips Semiconductors Datasheet, “74HC/HCT9323A Programmable ripple counter with oscillator”, Oct. 27, 1995.
Michael Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar, “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories”, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2000.
“Automatic Cache Line Access Monitoring” IBM TDB, vol. 37, No. 6A, Jun. 1994, p. 299.
K. Stein, et al., “Storage Array and Sense/Refresh Circuit for Single Transistor Memory Cells”, IEEE Journal of Solid State Circuits, vol. SC-7, No. 5, 336-340 (Oct. 1972).
K. Stein, et al., Session V: Memory II, “Storage Array and Sense/Refresh Circuit for Single Transistor Memory Cells”, IEEE International of Solid State Circuits conference, 1972, pp. 56-57.
“Automatic Cache Line Access Monitoring” IBM TDB, vol. 37, No. 6A, p. 299 (Jun. 1994).
Burger et al., “The Declining Effectiveness of Dynamic Caching for General-Purpose Microporcessors,” University of Wisconsin-Madison, CS TR #1261 (1995).
Kaxiras et al., “Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power,” ISCA (2001).
Kaxiras et al, “Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power,” First International Workshop on Power-Aware Computer Systems (PACS) (Nov. 12, 2000).
Phillips Semiconductors Datasheet, “74HC/HCT9323A Programmable Ripple Counter with Oscillator,” (Oct. 27, 1995).
Powell et al , “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) (Aug. 2000).
Stein et al , “Storage Array and Sense/Refresh Circuit for Single Transistor Memory Cells,” IEEE Journal of Solid State Circuits, vol. SC-7, No. 5, pp. 336-340 (Oct. 1972).
Stein et al , “Session V: Memory II, Storage Array and Sense/Refresh Circuit for Single Transistor Memory Cells” IEEE International of Solid State Circuits Conference, pp. 56-57 (1972).
Wood et al , “A Model for Estimating Trace-Simple Miss Ratios,” Proc of ACM Sigmetrics Conf on Measurement and Modeling of Computer Systems (May 1991).
Yang et al. An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches Proc of the Seventh Int'l Symposium on High-Performance Computer Architecture (HPCA) (2001).
Powell et al., “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories,” Purdue University, ISLPED '00, Rapallo, Italy, (2000).
Wood et al., “A Model for Estimating Trace-Sample Miss Ratios,” Proc. of ACM Sigmetrics Conf. on Measurement and Modeling of Computer Systems, (May 1991).
Yang et al., “An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches,” Proc. of the Seventh Int'l Symposium on High-Performance Computer Architecture (HPCA), (2001).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for reducing leakage power in a cache... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for reducing leakage power in a cache..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing leakage power in a cache... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4048308

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.