Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2002-06-21
2004-08-10
Fleming, Fritz (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S039000, C710S113000, C712S225000, C711S112000, C711S168000
Reexamination Certificate
active
06775717
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to direct memory access (“DMA”) and in particular, to a method and apparatus for reducing latency due to set up time between DMA transfers.
BACKGROUND OF THE INVENTION
FIGS. 1 and 2
illustrate a conventional DMA technique performed by a conventional DMA controller, resulting in latency due to set up time between DMA transfers. As shown in
FIG. 1
, in
102
, if a DMA grant is received from an arbiter that arbitrates DMA requests from multiple DMA channel interfaces, then, in
103
, a DMA transfer through the winning DMA channel interface is initiated by first performing conventional set up activities before transferring data. In
104
~
106
, the DMA transfer is then performed. If a transmission error occurs before completion of the DMA transfer, then in
105
, the DMA transfer is aborted and in
101
, the DMA controller goes into an idle state waiting for the next DMA grant. On the other hand, in
106
, if the DMA transfer happens to finish error free, then jumping back to
101
, the DMA controller goes into an idle state waiting for the next DMA grant so that each of
102
~
106
can once again be performed for a next DMA transfer.
As shown in
FIG. 2
, the conventional DMA technique for the conventional DMA controller results in latency due to set up time between DMA transfers. The latency has two components. The first component is a set up time T1 associated with the DMA controller which represents a delay between the time that the DMA controller receives the DMA grant from the arbiter and the time that address and command information is provided to a memory controller controlling a memory participating in the DMA. The second component is a set up time T2 associated with the memory and memory controller which represents a delay between the time the memory controller receives the address and command information from the DMA controller and the time that data is read from or written to the memory in response to the address and command information.
Procedurally, a first grant is received, and after set up delay T1, address and command information are provided to the memory controller. The memory controller then provides the address and command information to a memory, and after another set up delay T2, data is read from or written to the memory. At the end of the DMA transfer, a done indication is generated, and in response, the arbiter performs another arbitration, resulting in a second grant to the same or another DMA channel. The second DMA transfer then goes through the same set up times T1 and T2 before data is transferred between the memory and the DMA channel interface participating in the second DMA transfer.
As can be readily appreciated, repetitions of the set up times T1 and T2 between successive DMA transfers considerably slows down the transmission rate through the DMA channels, thus reducing the benefits of high speed DMA channel interfaces.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for reducing latency due to set up time between DMA transfers.
Another object is to provide an apparatus for reducing latency due to set up time between DMA transfers.
These and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is a method for reducing latency due to set up time between DMA transfers, comprising: initiating arbitration of DMA channel requests prior to completion of a current DMA transfer; and initiating set up for a next DMA transfer prior to completion of the current DMA transfer according to the arbitration so as to reduce latency due to set up time between the current DMA transfer and the next DMA transfer.
Another aspect is a method for reducing latency due to set up time between DMA transfers, comprising: arbitrating pending DMA channel requests before completion of a current DMA transfer; setting up for a next DMA transfer prior to completion of the current DMA transfer according to the arbitration; and performing the next DMA transfer immediately after completion of the current DMA transfer provided the setting up for the next DMA transfer has completed.
Still another aspect is an apparatus for reducing latency due to set up time between DMA transfers, comprising: a DMA channel interface providing a series of DMA channel requests such that a DMA channel request for a next DMA transfer is provided by the DMA channel interface before a current DMA transfer is completed; and a DMA controller initiating arbitration of DMA channel requests after the DMA channel request for the next DMA transfer is provided by the DMA channel interface and before the current DMA transfer is completed, and initiating set up for the next DMA transfer prior to completion of the current DMA transfer according to the arbitration so as to reduce latency due to set up time between the current DMA transfer and the next DMA transfer.
Yet another aspect is an apparatus for reducing latency due to set up time between DMA transfers, comprising: a first DMA channel interface participating in a current DMA transfer; a second DMA channel interface providing a DMA channel request for a next DMA transfer before the current DMA transfer is completed; and a DMA controller initiating arbitration of DMA channel requests after the DMA channel request for the next DMA transfer is provided by the second DMA channel interface and before the current DMA transfer is completed, and initiating set up for the next DMA transfer prior to completion of the current DMA transfer according to the arbitration so as to reduce latency due to set up time between the current DMA transfer and the next DMA transfer.
Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiment, which description should be taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5245575 (1993-09-01), Sasaki et al.
patent: 5423020 (1995-06-01), Vojnovich
patent: 5630171 (1997-05-01), Chejlava, Jr. et al.
patent: 5900865 (1999-05-01), Howe
patent: 6055583 (2000-04-01), Robbins
patent: 6108722 (2000-08-01), Troeller et al.
Liao Jiann
Tang Ming
Fleming Fritz
Integrated Device Technology Inc.
Mai RiJue
Okumoto Victor H.
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