Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-09-13
2003-03-18
Nguyen, Vinh P. (Department: 2829)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Combined with the removal of material by nonchemical means
Reexamination Certificate
active
06534419
ABSTRACT:
FIELD OF THE INVENTION
The present invention is in the field of semiconductor and printed-circuit-board (PCB) manufacturing including surface mount technologies (SMT), and pertains more particularly to methods and apparatus for strengthening structures while reducing mass and thickness.
BACKGROUND OF THE INVENTION
The field of integrated circuit interconnection and packaging is one of the most rapidly-evolving technologies associated with semiconductor manufacturing. As demand for devices that are smaller and more powerful continues to increase, pressures are put on manufacturers to develop better and more efficient ways to assemble and package IC products. One of the more recently developed methods for assembling and packaging IC products is known as Ball-Grid-Array (BGA) technology. Motorola™ inc. is one of the noted pioneers of BGA technology. Currently there are many companies that license BGA technology developed by Motorola™, and Motorola and other companies continue to develop BGA technology.
BGA technology provides several advantages over more mainstream technologies such as Fine-Pitch-Technology (FTP), and Pin-Grid-Array (PGA). One obvious advantage is that there are no leads that can be damaged during handling. Another obvious advantage is that the solder balls are typically self-centering on die pads. Still other advantages are smaller size, better thermal and electrical performances, better package yields, and so on.
In BGA technology, wafers or substrates are typically protected with a non-conductive material such as a nitride layer. The die pads are exposed through the nitride layer by means of chemical etching, or by other known methods. The protective nitride layer is intended to protect the substrates from contaminants and damage. One problem with prior-art protective coatings such as a nitride layer is that it is ultra-thin and does not offer any protection to the die pads themselves nor to the connection points between solder balls in the die pads.
It has occurred in the inventor that an additional protective coating, such as a protective polymer-based coating, would offer a measure of protection not provided with prior-art coatings. For example, it is desired that in addition to protecting the substrates itself, die pads and soldered connections may also benefit logically from protection. However, in order to obtain the added, protective benefits from an additional coating, a unique application process must be conceived. It is to such a process that the method and apparatus of the present invention is directed.
In the development of protective coating technology for BGA devices and other contact schemes the inventors have also discovered that a similar technique also provides vastly increased lateral strength for connections made to connection pads on BGA assemblies and other sorts of devices wherein connection extensions to pads are necessary. The unique coatings also provide additional rigidity for devices, both while devices (dies) are still joined on a wafer before separation, and after the die are separated. The inventors have discovered that the benefits of the strengthening are such that silicon thickness can be reduced significantly after the application of such a coating, reducing overall die thickness and also mass, as well as thermal mass.
SUMMARY OF THE INVENTION
In a preferred embodiment of the present invention a method for decreasing the mass and increasing the strength of an IC wafer assembly is provided, comprising the steps of (a) adding a polymer coating to the frontside of the wafer assembly to protect and strengthen, and (b) removing silicon material from the backside of the wafer assembly, reducing the overall thickness of the assembly.
In preferred embodiments, in step (b), the silicon material is removed by grinding. Also in preferred embodiments the polymer layer may be applied by one of screening, spraying, dispense and spinning, or injection into a mold.
In some cases steps are provided for adding contact extensions to contact regions before adding the polymer coating, and planarizing the polymer coating after addition to expose the contact extensions. In some of these embodiments there is a step for adding second contact extensions from the exposed contact extensions after planarizing.
In another aspect of the invention an IC die is provided, comprising contact extensions added to contact regions on a front surface at contact interfaces, a polymer layer on the front surface supporting, protecting and strengthening the extensions and contact interfaces, and a silicon portion having a thickness significantly less than conventional silicon-based dies. In some cases thickness of the silicon portion is less than the thickness of the polymer layer.
In various embodiments of the present invention taught in enabling detail below, for the first time a method is provided whereby contacts added to IC die, resulting in an interface typically of dissimilar materials, may be protected and strengthened, and the overall thickness of such die may then be reduced, providing significant advantages.
REFERENCES:
patent: 6008070 (1999-12-01), Farnworth
Advanced Interconnect Solutions
Boys Donald R.
Central Coast Patent Agency Inc.
Kilday Lisa
Nguyen Vinh P.
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