Method and apparatus for reduced pin count package...

Data processing: measuring – calibrating – or testing – Testing system – Of circuit

Reexamination Certificate

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C702S118000

Reexamination Certificate

active

06931346

ABSTRACT:
A method and apparatus for testing the chip-to-package connectivity of a common I/O of a semiconductor chip is disclosed which uses reduced pin count testing methods. The method includes driving a test signal transition onto a control pad of a semiconductor chip with a weak driver and comparing the transition rise time with a threshold value. For an I/O with a faulty chip-to-package connection, the rise time is much faster than for an I/O with a completed chip-to-package connection. Additional impedances may also be added to the tester fixturing to increase the sensitivity of the test equipment to the capacitance of the I/O connections.

REFERENCES:
patent: 4504783 (1985-03-01), Zasio et al.
patent: 4565966 (1986-01-01), Burr et al.
patent: 5241264 (1993-08-01), Nishiura
patent: 5266901 (1993-11-01), Woo
patent: 5268645 (1993-12-01), Prokoff et al.
patent: 5278841 (1994-01-01), Myers
patent: 5502392 (1996-03-01), Arjavalingam et al.
patent: 5509019 (1996-04-01), Yamamura
patent: 5602989 (1997-02-01), Aria
patent: 5736862 (1998-04-01), Hamblin
patent: 5923676 (1999-07-01), Sunter et al.
patent: 5974476 (1999-10-01), Lin et al.
patent: 6020752 (2000-02-01), Shimasaki
patent: 6057698 (2000-05-01), Heo et al.
patent: 6058496 (2000-05-01), Gillis et al.
patent: 6107814 (2000-08-01), Martin
patent: 6260163 (2001-07-01), Lacroix et al.
patent: 6262580 (2001-07-01), Wu
patent: 6292415 (2001-09-01), Brehm
patent: 6397361 (2002-05-01), Saitoh
patent: 2002/0079926 (2002-06-01), Haycock et al.
patent: 2002/0169588 (2002-11-01), Grupp et al.
IBM Technical Disclosure Bulletin, vol. 37, No. 9, Sep. 1994, Interconnect Verification Method for Boards, pp. 299-302.
IBM Technical Disclosure Bulletin, vol. 8, No. 11, Apr. 1966, “Measurement of Impedances Under Dynamic Pulse Conditions”, pp. 1507-1510.

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