Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-08-22
2004-04-20
Tang, Minh N. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C714S724000
Reexamination Certificate
active
06724210
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to a method and apparatus for testing semiconductor chip devices and, more particularly, to a method and apparatus for verifying the connectivity of chip-to-package input/outputs (I/Os) on a high speed semiconductor chip having a common I/O, also known as bidirectional I/O (BIDI).
2. Background Art
In the testing of semiconductor chip devices, such as application specific integrated circuits (ASICs) and/or microprocessors with high speed I/Os, a variety of tests are performed to ensure proper functionality and connectivity. These tests may include, for example, time interval tests for particular semiconductor chip functions (i.e. access, setup, and hold times), and connectivity tests to determine the connectivity of a semiconductor device chip to the semiconductor device package. Conventionally, testing of a semiconductor device requires a direct connection by test equipment to each package I/O to complete all necessary tests.
With conventional semiconductor chip testing technology, time intervals are measured by a tester external to the semiconductor chip, wherein the tester provides appropriate testing signals and measures corresponding response times for a particular tested function. The particular semiconductor chip device is then characterized and classified based upon the measured response time. Testing of semiconductor chip I/Os has historically been performed with a physical tester/DUT (device under test) interface and an appropriate set of test signal patterns, waveforms, and timings created by a tester in accordance with a particular semiconductor device or chip testing procedure.
U.S. Pat. No. 6,058,496 to Gillis et al. (May 2, 2000) (hereinafter sometimes referred to as “Gillis”), the disclosure of which is hereby incorporated herein by reference, is assigned with the present invention to a common assignee. Gillis discloses a SELF TIMED AC CIO WRAP METHOD AND APPARATUS for testing a semiconductor chip. The invention of Gillis relates to a semiconductor chip with a common or bidirectional I/O pad which is electrically coupled to an off-chip driver and an off-chip receiver associated with a tester. A common I/O refers to a type of semiconductor device I/O which has both a driver and a receiver connected to the same physical pad on the device.
FIG. 2
of Gillis is included as
FIG. 1
herein. As shown in
FIG. 1
herein, Gillis discloses and describes an invention which includes an external tester-generated launch clock
90
and a capture clock
92
which are used in AC CIO Wrap delay fault testing. The Gillis invention also includes tester drivers
102
and
104
, fixturing
106
and
108
, a semiconductor device pad C-
4
, a launch latch
112
, an observation latch
114
, a clock tree
100
, a semiconductor chip driver
94
and a semiconductor chip receiver
96
.
For the AC CIO Wrap testing method for the device shown in
FIG. 1
, the tester launches or triggers a “rising” or “falling” edge which propagates through the I/O to check for AC delay defects in the I/O. An “error” in the measurement is characterized by tester driver skew plus the error in the on-chip clock tree
100
fanout. The tester is not coupled to the output C-
4
pad of the CIO being tested. Clock trees are shown in the FIG. to indicate that there can be a fanout of clocks and clock signals. The clocks from the clock trees may couple to multiple latches on the chip other than those shown. With LSSD (Level Sensitive Scan Delay), one clock tree feeds the L
1
latches and a different clock tree feeds the L
2
latches. In this way, the timing of I/Os may be tested without directly coupling a test probe to every I/O.
Conventional semiconductor device testing methods, including those disclosed in Gillis, however, do not provide a means by which a semiconductor device may be tested for package connectivity on the same testing equipment that other testing is performed. Under conventional methods, each semiconductor device must be tested for chip-to-package connectivity using separate testing equipment with test probes directly coupled to and testing each package I/O. Transfer of the semiconductor device to new testing equipment and testing each individual I/O requires additional time and cost in the testing process.
It would thus be desirable to provide a method and apparatus for verifying package connectivity for a semiconductor device which does not require transfer to additional testing equipment or connection to each individual package I/O.
DISCLOSURE OF THE INVENTION
The present invention provides a method and apparatus for measuring a rise time of a first test signal transition to determine whether a chip-to-package connection associated with an I/O of a semiconductor device is faulty. The present invention further provides a method and apparatus for measuring a rise time of a common I/O on-chip driver/on-chip receiver pair through a chip I/O without use of an external tester contact to the chip I/O pad.
In a first embodiment of the invention, a semiconductor device tester is disclosed having a driver with a weak driver impedance to drive a test signal transition to an I/O of a semiconductor device through a control pad of the semiconductor device. By driving a test signal transition with a weak driver, the response of the test signal transition is more sensitive to the capacitance associated with the semiconductor device. One or more characteristics of the response of the test signal transition are evaluated to determine whether a chip-to-package connection associated with the I/O is faulty. The impedance may also be switchably or variably coupled to the driver so that the driver may be used for other testing procedures in which a weak driver is undesirable.
To determine if a chip-to-package connection associated with a particular I/O is faulty, comparison may be made between one or more characteristics of the I/O and a connectivity threshold value. The connectivity threshold value may be determined as a predetermined ideal value, or from comparison with one or more characteristics of another I/O. In a particular embodiment, the RC constant of the transition response for a first I/O is compared to an RC constant connectivity threshold value to determine if the chip-to-package connection associated with the first I/O is faulty. If the RC constant of the transition response for the first I/O is greater than the RC constant connectivity threshold, the chip-to-package connection associated with the first I/O is identified as being faulty. The RC constant of the transition response may be determined by triggering a first latch at the start of a transition test signal, triggering a second latch when the transition test signal has risen to a predetermined threshold value, and calculating the rise time from the difference in the trigger times of the first and second latches.
In another embodiment of the invention, a fixture impedance is added to the tester device of the first embodiment between test fixturing and a semiconductor device to be tested. The fixture impedance added may improve the visibility of the effects of the weak driver impedance. In one particular embodiment, the fixture impedance is a 10 pf capacitor coupled in series with the test fixturing. The fixture impedance may also be configured as a switchable or variable impedance.
REFERENCES:
patent: 4565966 (1986-01-01), Burr et al.
patent: 5241264 (1993-08-01), Nishiura
patent: 5266901 (1993-11-01), Woo
patent: 5268645 (1993-12-01), Prokoff et al.
patent: 5278841 (1994-01-01), Myers
patent: 5502392 (1996-03-01), Arjavalingam et al.
patent: 5602989 (1997-02-01), Aria
patent: 5736862 (1998-04-01), Hamblin
patent: 5923676 (1999-07-01), Sunter et al.
patent: 6020752 (2000-02-01), Shimasaki
patent: 6058496 (2000-05-01), Gillis et al.
patent: 6260163 (2001-07-01), Lacroix et al.
patent: 6397361 (2002-05-01), Saitoh
IBM Technical Disclosure Bulletin, vol. 37, No. 9, Sep. 1994, Interconnect Verification Method for Boards, pp. 299-302.
IBM Technical Disclosure Bulletin
Combs Michael L.
Wheater Donald L.
Tang Minh N.
Walsh Robert A.
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