Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2000-08-31
2004-03-09
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000, C713S500000, C713S600000
Reexamination Certificate
active
06704881
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to synchronizing the timing of data transfer with a system clock using a delay lock loop circuit. More particularly, the present invention relates to a method and apparatus for producing a symmetrical data clock by adding to or subtracting compensating delays to the falling edge of an internal clock.
BACKGROUND OF THE INVENTION
Modern high-speed integrated circuit devices, such as synchronous dynamic random access memories (SDRAM), microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through, and out of the devices. Additionally, new types of circuit architectures such as SLDRAM require individual circuits to work in unison even though such circuits may individually operate at different speeds. As a result, the ability to synchronize the operation of a circuit through the generation of local clock signals has become increasingly more important. Conventionally, data transfer operations are initiated at the edges of the local clock signals (i.e., transitions from high to low or low to high).
In synchronous systems, integrated circuits are synchronized to a common reference system clock. This synchronization often cannot be achieved simply by distributing a single system clock to each of the integrated circuits for the following reason, among others. When an integrated circuit receives a system clock, the circuit often must condition the system clock before the circuit can use the clock. For example, the circuit may buffer the incoming system clock or may convert the incoming system clock from one voltage level to another. This processing introduces its own delay and/or skew, with the result that the locally processed system clock, often will no longer be adequately synchronized with the incoming system clock. In addition, the system clock itself may have a certain amount of skew within a tolerance set by system specifications. For example, an exemplary DDR SDRAM system may allow a system clock skewed to have a duty cycle of 55%/45%. The trend towards faster system clock speeds further aggravates this problem since faster clock speeds reduce the amount of delay, or clock skew, which can be tolerated.
To remedy this problem, an additional circuit is conventionally used to synchronize the locally processed clock to the system clock. Two common circuits which are used for this purpose are the phase-locked loop (PLL) and the delay-locked loop (DLL). In the phase-locked loop (PLL), a voltage-controlled oscillator produces the local clock. The phases of the local clock and the system clock are compared by a phase-frequency detector, with the resulting error signal used to drive the voltage-controlled oscillator via a loop filter. The feedback via the loop filter phase locks the local clock to the system clock.
In contrast, the delay-locked loop (DLL) generates a synchronized local clock by delaying the incoming system clock by an integer number of periods. More specifically, the buffers, voltage level converters, etc. of the integrated circuit device, for example the input buffers of an SDRAM memory device, introduce a certain amount of delay. The delay-locked loop (DLL) then introduces an additional amount of delay such that the resulting local clock is synchronous with the incoming system clock.
In certain synchronous circuit devices, for example double data rate(DDR) dynamic random access memory (DRAM), wherein operations are initiated on both the rising and the falling edges of the clock signals, it is known to employ a delay lock loop (DLL) to synchronize the output data with the system clock (XCLK) using a phase detector. In an exemplary case, the transition of the data signal is perfectly aligned with the rising or falling edge of the XCLK. The time from the rising or falling edge of the data clock to the time when the data is available on the output data bus (tAC) is within specifications. A phase detector is conventionally used to lock the rising edge of the output data signal from the DLL (DQ) to the rising edge of the XCLK. Since the rising edge of the DQ signal is phase-locked to the rising edge of the XCLK signal, the rising edge of data being output from the device is synchronized with the system clock XCLK.
FIG. 1
depicts a DDR DRAM data synchronizing circuit using a DLL as is presently contemplated in the art. A DQ data output signal from an array is input to output buffer
23
and has its timing adjusted to be synchronized with the XCLK signal
8
. At system initialization, a phase detector
2
is activated by an initialization signal
4
. The phase detector
2
compares the phase of the CLKIN signal
6
, a processed signal derived from the XCLK signal
8
, with the OUT_MDL signal
10
, a model of the data output signal DQ. The phase detector
2
then adjusts the DLL delay elements
12
using respective ShiftR
14
and ShiftL
16
signals, to respectively decrease or increase the time delay added to the CLKIN signal
6
with respect to the OUT_MDL signal
10
.
The Output Buffer Model
19
models the delays generated by the Output Buffer
23
and the CLK Buffer Model
21
models the delays generated by the Input Buffer
7
to produce an OUT_MDL signal
10
such that alignment of the OUT_MDL signal
10
with the CLKIN signal
6
will result in alignment of the XCLK signal
8
with the DQ data output signal
24
. By adjusting the delay of the CLKIN signal
6
through the DLL delay elements
12
, the phase detector
2
can align the rising edge of the DQ output signal
24
with the rising edge of the XCLK signal
8
.
The output data signal DQ
24
is provided to a data pad
31
and is synchronized with the system clock XCLK
8
.
In addition, the
FIG. 1
circuit can also be used to adjust an output toggle clock signal DQS as shown in FIG.
9
. In this case, an additional output buffer
23
a
is used to generate the DQS signal at pad
31
a
. The DQS signal can be used for timing purposes, such as a data strobe signal. For purposes of simplifying the discussion below, the background discussion and the discussion of the invention will be described in the context of synchronizing the data output signal DQ with the system clock XCLK
8
, but the discussions herein apply to also synchronizing a DQS signal with the system clock XCLK.
FIG. 2
is a timing diagram for the synchronizing circuitry of FIG.
1
. As shown in
FIG. 2
, the rising edge
26
of the XCLK signal
9
, which is carried on the XCLK signal line
8
of
FIG. 1
, is aligned with the rising edge
28
of the DQ signal
25
, which is carried on the DQ signal line
24
of FIG.
1
. As is indicated by the arrows shown in
FIG. 2
, the rising edge
30
of the DLLCLK signal
33
(carried on the DLLCLK signal line
32
of
FIG. 1
) initiates the rise and fall of the DLLR signal
21
(carried on the DLLR signal line
20
of FIG.
1
), through the Rise Fall CLK Generator
18
(FIG.
1
), which in turn initiates the rising edge
28
of the DQ signal
25
. Likewise, the rising edge
34
of the DLLCLK* signal
37
(carried on the DLLCLK* signal line
36
) initiates the rise and fall of the DLLF signal
23
(carried on the DLLF signal line
22
of
FIG. 1
) which in turn initiates the falling edge
42
of the DQ signal
25
. For proper data synchronization, the rising edges of the XCLK
9
and DQ
25
should be aligned within an allowed tolerance and the duty cycle of the data output timing signal DQ
25
should be within the specifications for the system in which the synchronizing circuitry will be used.
Unfortunately, however, not all synchronizing circuitry components are ideal or even exemplary. Non-symmetrical delays can be created by the input processing of the system clock including input buffering of the system clock signal using the buffer
7
. The system clock itself may exhibit an asymmetric duty cycle, for example, up to a 55/45 duty cycle for a typical SDRAM. Variations in layout, fabrication processes, operating temperatures and voltages, and the like, result in non-symmetrical delays among the D
Baker R. Jacob
Li Wen
Schoenfeld Aaron
Butler Dennis M.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Patel Nitin C
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