Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1999-07-19
2002-05-14
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S201000, C710S200000
Reexamination Certificate
active
06389519
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to a method and apparatus employing multiple processors, and more particularly to a method and apparatus for facilitating access to shared memory addresses over a common bus by a plurality of data processors.
BACKGROUND OF THE INVENTION
Multiprocessor systems are well known. For example, a multimedia computer system may have a plurality of data processors such as a host processor, a graphics and video processor, and other processors. These processors may be on the same or separate chips and may share one or more buses. A problem arises with systems employing multiple processors when the multiple processors need to access shared memory addresses over a common bus. If the processors are not properly controlled, one processor may overwrite data in an address that is being accessed by another processor prior to the second processor finishing use of the data at the address.
One solution has been to employ address locking. In such systems, addresses are locked so that only one processor at a time can read or write to a given address. For example, when a processor needs to read data that is stored in a particular address, the processor needing access to the address may send a command to a host processor or other device to lock the address so that no other processors can access the address until the processor needing access has completed its task. However, a problem can arise with systems that use unaligned addressing structures. For example, when a processor needs to read data that is stored in misaligned addresses, the processor typically has to perform two separate transactions to complete the address lock transaction. During this time, another processor can lock the needed address when the address is on the boundary. This is typically because the processor can only read memory addresses that are aligned to an eight byte boundary, for example. Accordingly, a different solution has been implemented, sometimes referred to as bus locking.
With bus locking, a processor locks the bus to prevent other processors from accessing a desired address. However, bus locking can be inefficient since other processors cannot complete their tasks until the processor that has locked the bus has unlocked the bus. This can result in hundreds of cycles being lost. This becomes a greater problem when real time interrupts are being used such as in the case of multimedia processors that process video data, audio data and other real time data. For example, a processor that is processing real time audio may drop audio or video frames if the bus is locked for a larger period of time than suitable overflow buffers can accommodate.
Consequently, there exists a need for a method and apparatus for facilitating access to shared memory addresses, over a common bus, by a plurality of data processors that overcomes one or more of the above-mentioned problems.
REFERENCES:
patent: 5185865 (1993-02-01), Pugh
patent: 5787486 (1998-07-01), Chin et al.
patent: 5797026 (1998-08-01), Rhodehamel et al.
Patkar Niteen
Thusoo Shalesh
ATI International SRL
Tran Denise
Vedder Price Kaufman & Kammholz
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