Method and apparatus for providing adjustable latency for...

Details Method and apparatus for providing adjustable latency for... Method and apparatus for providing adjustable latency for...

2006-11-21

2006-11-21

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S048000, C714S733000, C365S201000

Reexamination Certificate

active

07139943

ABSTRACT:
An integrated circuit includes a core memory array and a test mode compression circuit. The test mode compression circuit receives test mode data from the core memory array. A multiplexer receives read data from the core memory array and test mode data from the test mode compression circuit. The multiplexer receives a test mode compression signal and selectively transfers one of the read data and the test mode data dependent at least in part upon the test mode compression signal.

REFERENCES:
patent: 6014759 (2000-01-01), Manning
patent: 6286115 (2001-09-01), Stubbs
patent: 6360340 (2002-03-01), Brown et al.
patent: 6438048 (2002-08-01), Kumar
patent: 6584025 (2003-06-01), Roohparvar et al.

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