Method and apparatus for providing accurate T(on) and T(off) tim

Details Method and apparatus for providing accurate T(on) and T(off) tim Method and apparatus for providing accurate T(on) and T(off) tim

1993-10-29

1996-03-19

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365194, 327263, G11C 700

Patent

active

055008186

ABSTRACT:
A frame buffer including an array of memory cells, circuitry for accessing the memory cells to derive selected pixel data, and output circuitry for providing data signals at an output port, the output circuitry including circuitry for determining the precise time required for a data signal to rise and fall at the output port, such circuitry being selected to provide the minimum delay between succeeding data signals at the output port.

REFERENCES:
patent: 4661928 (1987-04-01), Yasuoka
patent: 4802127 (1989-01-01), Akaogi et al.
patent: 4833657 (1989-05-01), Tanaka
patent: 5130564 (1992-07-01), Sin
patent: 5164621 (1992-11-01), Miyamoto
patent: 5313422 (1994-05-01), Houston

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