Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Patent
1997-12-04
1999-10-05
Palys, Joseph E.
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
713501, G06F 172
Patent
active
059616490
ABSTRACT:
A method of transmitting a signal from a relatively fast clock domain to a relatively slow clock domain is described. The fast and slow clock domains operate according to respective fast and slow clock signals that are substantially synchronized and that have respective frequencies that are non-integer multiples. A first state of an input signal is latched at the commencement of a first period of the fast clock signal, the commencement of the first period of the fast clock signal being substantially coincident with the commencement of a first period of the slow clock signal. In response to the latching of the first state of the input signal, a first output signal is generated and held over the first period, and at least one further period, of the fast clock signal. The first output signal is then latched in the second time domain in response to the commencement of a second period of the slow clock signal, the second period being immediately subsequent to the first period of the slow clock signal.
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Gadagkar Ashish S.
Khandekar Narendra
Kubick Robert F.
Muthal Manish
VonBokern Vincent E.
Hossain Abu
Intel Corporation
Palys Joseph E.
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