Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-01-31
2004-02-24
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S401000
Reexamination Certificate
active
06697956
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method for synchronising a network, and particularly but not exclusively to a method for synchronising the clock frequencies of microcontrollers in a distributed microcontroller network.
BACKGROUND OF THE INVENTION
Distributed microcontroller systems are used widely in many fields, and increasingly so in automotive electronics applications. One example of such use is in electronic braking systems, which dispense with mechanical or hydraulic linkages and instead employ a communications bus which exchanges data between a driver operated actuator (brake pedal) and brake actuators attached to vehicle wheels. These actuators each have a microcontroller arranged to send and receive messages on the bus, for controlling the braking function of the vehicle.
It is important in a real-time application such as the so-called ‘brake-by-wire’ system mentioned above, that the clock frequencies of the microcontrollers are synchronised, such that a real-time measurement (such as the speed of a vehicle wheel) can be properly combined with other real-time measurements (such as the speed of the other wheels) in order to provide appropriate control functions for the system. Furthermore real-time instructions, such as an instruction to apply a brake at the nodes, should be executed at each of the nodes at the same time, otherwise differential forces acting upon the vehicle may cause it to become unbalanced during breaking.
A number of solutions exist for providing time synchronisation across a distributed network. In one example, all processing elements (microcontrollers) share a common clock, which is provided via the bus. A problem with this arrangement is that signal integrity and available data bandwidth are compromised. Furthermore, Electromagnetic Interference (EMI) is greatly increased when the processing elements are not co-located. These problems worsen as the distance between processing elements increases.
A second known solution employs dedicated synchronisation data messages transmitted on the bus. These are provided at regular intervals to ensure time synchronisation, and therefore negatively effect the available bandwidth on the bus available for control data.
These methods provide some degree of fault detection and fault tolerance, but with a significant overhead in terms of cost (for duplicate and redundant hardware), complexity and bandwidth.
This invention seeks to provide a synchronisation arrangement and method which mitigate the above mentioned disadvantages.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a synchronisation arrangement for a distributed microcontroller network, comprising: a plurality of distributed microcontrollers, each having an internal clock frequency and a frequency correction arrangement coupled to selectively adjust the internal clock frequency, each of the microcontrollers being further arranged to transmit data signals via the network, the data signals having periodic logic level transitions which are substantially synchronised to the internal clock frequency of the microcontroller, wherein each of the plurality of microcontrollers is arranged to selectively adjust its internal clock frequency in dependence upon a phase difference between the internal clock frequency and the logic level transitions of the data signals received via the network, such that the clock frequencies of the plurality of microcontrollers become substantially phase-synchronised.
According to a second aspect of the present invention there is provided a method for synchronising internal clock frequencies of a plurality of microcontrollers in a distributed microcontroller network, comprising the steps of: exchanging data signals between the plurality of microcontrollers via the network, the data signals having periodic logic level transitions which are substantially synchronised to the internal clock frequency of the microcontroller, adjusting the internal clock frequency of each of the microcontrollers in dependence upon a phase difference between the internal clock frequency and the logic level transitions of the data signals received via the network, such that the clock frequencies of the plurality of microcontrollers become substantially phase-synchronised.
Preferably the distributed microcontroller network is incorporated in an automobile, and the distributed microcontroller network is a brake-by-wire automobile braking system.
In this way synchronisation is readily achieved in a distributed microcontroller network, without duplicate and redundant hardware and in a relatively simple manner.
REFERENCES:
patent: 3555194 (1971-01-01), Goto
patent: 3599110 (1971-08-01), Gindi
patent: 3815100 (1974-06-01), Winchester et al.
patent: 4064486 (1977-12-01), Faber
patent: 5726650 (1998-03-01), Yeoh et al.
Lee Thomas
Motorola Inc.
Yanchus, III Paul
LandOfFree
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