Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1996-12-26
2000-02-29
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
365201, G01R 3128
Patent
active
060322780
ABSTRACT:
A method and apparatus for providing a scan cell having a first input coupled to receive a data, a data output and a scan output. The scan cell being capable of transferring data to said scan output in response to a first scan clock and a second scan clock without requiring any timing-sensitive control signals.
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Gruner Fred
Parvathala Praveen
Beausoliel, Jr. Robert W.
Intel Corporation
Iqbal Nadeem
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