Method and apparatus for performing on-chip function checks and

Details Method and apparatus for performing on-chip function checks and Method and apparatus for performing on-chip function checks and

1998-01-21

2000-08-15

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714735, 714737, 714738, G01R 3128

Patent

active

061051551

ABSTRACT:
A method and apparatus in which on-chip functions are checked and any detected anomalies are located within a nested time interval. An on-chip function is tested by (1) applying a predetermined data pattern to the function, (2) computing a linear block error detection code residue from any output from the function being tested, and (3) comparing the residue to a error code residue (signature) derived from the output of a copy of the same function with the same data pattern. In one embodiment, the code signature has been previously derived from an error-free copy of the function. Where the signature is supplied contemporaneously by another copy of the same function also being tested, the function copy is not presumed error free. In both cases, any mismatch between the on-chip code residue and the signature indicates error, erasure, or fault. By either recursive reprocessing or shortening the intervals between comparisons, the mismatch can be located within a nested time or sequence interval.

REFERENCES:
patent: 5475694 (1995-12-01), Ivanov et al.
patent: 5638381 (1997-06-01), Cho et al.
patent: 5652754 (1997-07-01), Pizzica
patent: 5663967 (1997-09-01), Lindberg et al.
patent: 5671237 (1997-09-01), Zook
patent: 5675588 (1997-10-01), Maruyama et al.
patent: 5745500 (1998-04-01), Damarla et al.
patent: 5831988 (1998-11-01), Fagerness
A. S. Tanenbaum, "Distributed Operating Systems", Prentice Hall, Chapter 3, 1995, pp. 120-127.

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