Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-09-09
2008-09-09
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
11210302
ABSTRACT:
Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the invention is an improved DMA controller that automatically selects certain pin groups, which are connected to a common data bus, to receive test data words from a common data bus. By selecting more than one pin group at the same time, test data (such as a test data word) can be simultaneously loaded onto multiple pin cards at the same time. By loading this data into multiple pin cards at the same time, test data can be “fanned-out” to multiple pin cards and thereby be sent to multiple device sites at the same time. Another aspect of one embodiment of the invention utilizes DMA-based hardware to select which pin groups should received “fanned-out” test data. By utilizing DMA-based hardware to fan-out the test data, the software-based test programs and patterns may be created to manipulate a single device. The test program may select the number of sites to be tested and partition the tester resources to those sites. The DMA-based hardware and tester software will automatically fan-out the test data to all of the appropriate test sites.
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Very Low Cost Testers: Opportunities and Challenges, Bedsole et al., Motorola International Test Conference, IEEE Design & Test of Computers, 2001 IEEE, pp. 60-69.
Burke, Jr. Dennis Harold
Martel Michael Lee
Patel Gunvant T.
Brady III Wade James
Britt Cynthia
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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