Method and apparatus for performing high speed data transfers be

Details Method and apparatus for performing high speed data transfers be Method and apparatus for performing high speed data transfers be

1998-02-06

2000-05-02

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

710 23, 710 26, 345503, 345526, G06F 1328

Patent

active

060584386

ABSTRACT:
A system is provided for achieving high speed data transfers from a host memory to an ancillary processor, where the ancillary processor is preferably a geometry accelerator of a graphics machine. In accordance with a preferred embodiment, the system includes at least one memory segment having at least one enable bit and a starting address. The system further includes a data transfer queue defined in a portion of the host memory beginning at the starting location, where the data transfer queue has at least one header portion and at least one data portion, the header portion including at least one data ready bit that is indicative of whether the associated block of data is ready to be transferred to the ancillary processor. Finally, the system includes a controller, responsive to the enable bit, configured to transfer data directly from the data transfer queue to the ancillary processor, the controller being operative to evaluate the at least one data ready bit and transfer the associated block of data from the queue to the ancillary processor if the at least one data ready bit indicates that the data is ready for transfer.

REFERENCES:
patent: 5347634 (1994-09-01), Herrell et al.
patent: 5392391 (1995-02-01), Caulk, Jr. et al.
patent: 5404463 (1995-04-01), McGarvey
patent: 5448702 (1995-09-01), Garcia, Jr. et al.
patent: 5644784 (1997-07-01), Peek

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