Method and apparatus for performing equivalence checking on...

Details Method and apparatus for performing equivalence checking on... Method and apparatus for performing equivalence checking on...

2007-02-27

2009-11-24

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07624363

ABSTRACT:
A method for performing equivalence checking on logic circuit designs is disclosed. Within a composite netlist of an original version and a modified version of a logic circuit design, all level-sensitive sequential elements sensitized by a clock=0 are converted into buffers, and all level-sensitive sequential elements sensitized by a clock=1 are converted into level-sensitive registers. A subset of edge-sensitive sequential elements are selectively transformed into level-sensitive sequential elements by removing edge detection logic from the subset of the edge-sensitive sequential elements. A clock to the resulting sequential elements is then set to a logical “1” to verify the sequential equivalence of the transformed netlist.

REFERENCES:
patent: 6799308 (2004-09-01), You et al.
patent: 6874134 (2005-03-01), Collin et al.

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